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The following topics are dealt with: fault effects and self-checking techniques; BIST; technology robustness; reliability; innovative systems; innovative design; robustness; errors and latchup mitigation; secure circuits; fault detection; analog circuits; reliable systems; dependability analysis; and checkers and error correction.
Summary form only given. The proliferation of new terminals represents a major growth factor for the semiconductor industry. Multimedia mobile phones, game consoles, digital TV sets combine previously separated products and functions into a single box, often built around a single chip. This convergence of devices that integrate storage, security, multimedia, mobility, connectivity and computing on...
Summary form only given. This talk focuses on the challenges and opportunities of extending Moore's law from a radiation-induced soft error rate (SER) point of view. Driven primarily by power constraints and the economic need to scale, tomorrow's microprocessors will continue to integrate more cores and memory onto a roughly constant die area and to a lesser extend increase the clock frequency by...
Summary form only given. The quality of electrical tests during irradiation of components has also improved a lot. Test patterns have been modified and characteristics of recent DRAMs have had to be taken into account. We can also observe a trend in the results of soft error tests. In the beginning, we mostly got single-bit events and did not ask for more. The trend is now moving toward a complete...
With ongoing technology scaling, reliability is becoming increasingly important for integrated circuits (ICs) manufactured in deep-submicron CMOS technologies. The reliability issue that generally leads to the highest failure rates is that of radiation-induced soft errors. Both alpha particles, emitted by chip and package materials and cosmic neutrons are capable of inducing bit errors in ICs. These...
Summary form only given. With ever-shrinking process technology, there is significant concern about the effects of process variability on design margins, yield, and performance. In addition, reliability is a major concern with new technology, not only through classic means such as latent defects and NBTI, but also by new issues brought on by variability, small feature sizes, and power-saving features...
Summary form only given. Contrary to many other industrial processes, software production is characterized by an unusually high variance. This directly results from the significant role of the human factor in all the phases of its realization, and this will likely remain the case for a long time to come. In order to set the record straight, this presentation first analyzes various aspects of software...
In this paper, we demonstrate the need for considering the floorplan when the leakage power is calculated for a SoC. We proposed a leakage power estimation methodology which considers the floorplan of the SoC and the cycle-by-cycle dynamic power behavior while estimating leakage power. This methodology has been experimented with on three industrial SoC designs and we observed up to a 44.1% difference...
Summary form only given. Moore's law predicts that soon it will be possible to integrate billions of transistors on a single chip. Currently on-chip communication for multiprocessor system-on-chip (MPSoC) is realized using buses such as AMBA, STbus, and IBM's Core-connect. On-chip buses are not fundamentally different than computer buses, except that they are designed and optimized to operate entirely...
Summary form only given. It is amazing how chip level integration has progressed to this point that we now have chips that consist of more than a billion transistors. As amazing as this level of integration, we have only been exploiting 2 dimensions (2D) integration only, i.e. transistors are still on a common plane. Obviously, one way to surpass this 2D integration trend is to go three dimensions...
Summary form only given. Memories are the highest volume ICs. With production of 30K wafers/month, i.e., production of NAND flash memories with 800 chips/wafer, a single fab today produces more than 250M chips per year. In such a high volume manufacturing (HVM) environment, identification of recurring faults, determination and elimination of the root cause in real-time is paramount to un-interrupted...
FPGA emulation has proven to be a performance effective method to analyse the behaviour of digital circuits in the presence of soft errors due to SEU effects. In particular, the recently developed autonomous emulation techniques allow the classification of thousands and even millions of faults per second. In this paper, an approach to extend the autonomous emulation techniques to circuits with embedded...
Main stream scan test technology development has focused on a cost-efficient usage of external testers in conjunction with minimized on-chip pattern generators. Alternatively, an on-chip test processor that works with highly compacted test patterns from a ROM device allows a software-based self test procedure in the field of application, e.g. during startup tests. Furthermore, such an approach may...
This work presents a fault-tolerant version of the mass-produced 8-bit microprocessor M68HC11. It is able to tolerate single event transients (SETs) and single event upsets (SEUs). Based on triple modular redundancy (TMR) and time redundancy (TR) fault tolerance techniques, a protection scheme was implemented at high level in the sensitive areas of the microprocessor by using only standard gates in...
Systems on a chip (SoCs) in safety-critical applications need features such as built-in self-test, on-line self-test and error compensation of transient faults. With ever-shrinking feature size, also built-in self-repair (BISR) may become a must. While BIST and BISR are well understood and frequently implemented for embedded memory blocks, BISR for random logic is by far an unsolved problem. Logic...
Reconfigurable compute fabrics (RCFs) are cellular architectures in which an array of computing elements and a configurable interconnection fabric are combined with a general-purpose processor. RCFs can play an important role in safety- or mission-critical applications, provided that a clear understanding of their dependability is available. In this paper, we report an evaluation of the effects induced...
This paper describes a highly reliable digital circuit design method based on totally self checking blocks implemented in FPGAs. The bases of the self checking blocks are parity predictors. The parity predictor design method based on multiple parity groups is proposed. Proper parity groups are chosen in order to obtain minimal area overhead and to decrease the number of undetectable faults
Recently, various attacks have been proposed against many crypto systems, exploiting deliberate error injection during the computation process. In this paper, we add a residue-based error detection scheme to an RSA architecture to protect against such attacks. We then evaluate the error coverage and the expected area and latency overheads
This work intends to evaluate the effect of a single event upsets (SEUs) and crosstalk faults in a NoC router architecture by developing a fault injection mechanism, allowing an accurate analysis of the impact of SEU and crosstalk over the router service. Results show that such faults may affect the router behavior, causing loss of packets, errors in packet information or even compromising the router...
In this paper we show first that finding the location of a test vector in the sequence generated by an accumulator driven with an odd additive constant C is equivalent to the solution of a linear Diophantine equation with two variables. The latter equation is known to be solved fast in linear time. We then show that only one Diophantine equation needs to be solved per test set irrespective of the...
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