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We investigate the mechanism of the gate leakage current in the Si/SiO2/HfO2/TiN stacks in a wide temperature range (6 - 400 K) by simulating the electron transport using a multi-phonon trap assisted tunneling model. Good agreement between simulations and measurements allows indentifying the dominant physical processes controlling the temperature dependency of the gate current. In depletion/weak inversion,...
We present a novel fully differential input/output distributed transformer topology used for the design of millimeter-wave power amplifiers. Input/output distributed transformers are used to feed the input signal to four differential couples and to combine their output power. This topology improves the stability and the efficiency of the power amplifier, minimizing the chip area. The PA prototype...
This paper presents a novel low power boost converter designed and optimized to operate with a minimum input voltage as low as 250mV, which is the typical voltage range of novel micro energy sources. The low power budget of such energy sources (at most few hundreds of μWs) mandates the adoption of very efficient circuit solutions. The realized PCB prototype provides a regulated maximum output voltage...
A mechanism of degradation and breakdown in high-k/metal gate transistors was investigated. Based on the electrical test, physical analysis, and modeling results, we propose that the breakdown path formation/evolution in the interfacial SiO2 layer is associated with the growth of an oxygen-deficient filament facilitated by the grain boundaries of the overlaying high-k film. The model allows reproducing...
This paper investigates material and electrical properties of a new chalcogenide alloy for Phase-Change Memories (PCM): Carbon-doped GeTe (named GeTeC). First, several physico-chemical, optical and electrical analyses have been performed on full-sheet chalcogenide depositions in order to understand the intrinsic GeTeC phase-change behavior, and to characterize structure and composition of amorphous...
The systematic investigation of the role played by electrons and holes during the erase operation of TANOS memories by means of charge separation experiments and physics-based simulations is reported for the first time. We determined a dominance of electrons back-tunneling in the first part of the transient, and dominance of holes in the second part. Good agreement is reached between experimental...
Interface-trap effects are analyzed in inversion-type, self-aligned In0.53Ga0.47As and In0.53Ga0.47As/ In0.2Ga0.8As MOSFETs with ALD ZrO2 gate dielectric. Interface-trap densities in the order of 1013 cm-2 eV-1 are required to explain the measured subthreshold slopes. For these Dit values, donor-like interface traps are compatible with threshold-voltage values in the 0-0.15 V range as those observed...
In TANOS stuctures in retention, the major decrease in the programmed threshold voltage is found to be caused by the Vt sensing (IdVg measurements) rather than by intrinsic charge loss (when no bias is applied). This Vt decrease can be understood within the process of the temperature-activated charge transport through the Al2O3 blocking oxide. The charge loss can be minimized when Vt sensing time...
We demonstrate for the first time a fluorine incorporated band- engineered (BE) tunnel oxide (SiO2/HfSiO/SiO2) TANOS with excellent program / erase (P/E) characteristics and endurance to 105 cycles. Incorporating fluorine in the tunnel dielectric improves Si/SiO2 interface resulting in excellent endurance of nearly constant over 3 V P/E window for at least 105 cycles. Fluorine also reduces interface...
This article presents the analysis of the power efficiency of the inductive links used for remote powering of the biomedical implants by considering the effect of the load resistance on the efficiency. The optimum load condition for the inductive links is calculated from the analysis and the coils are optimized accordingly. A remote powering link topology with a matching network between the inductive...
In this paper we present a reconfigurable Class-E Power Amplifier (PA) whose operation frequency covers all uplink bands of GSM standard. We describe the circuit design strategy to reconfigure PA operation frequency maximizing the efficiency. Two dies, manufactured using CMOS and MEMS technologies, are assembled through bondwires in a SiP fashion. Prototypes deliver 20dBm output power with 38% and...
In this work we present a reconfigurable mid-power class-E power amplifier (PA) operating at ~900 MHz and ~1800 MHz (GSM standard) realized hybridizing one chip manufactured in AMS 0.35 mum CMOS technology and one MEMS sub-network. The CMOS chip realizes the active part of the circuit, whereas the MEMS block (realized in FBK technology) implements a reconfigurable impedance matching network (MN) that...
We apply a systematic approach to identify a high-k/metal gate stack degradation mechanism. Our results demonstrate that the SiO2 interfacial layer controls the overall degradation and breakdown of the high-k gate stacks stressed in inversion. Defects contributing to the gate stack degradation are associated with the high-k/metal-induced oxygen vacancies in the interfacial layer.
Low-frequency noise in PCM devices is experimentally investigated providing a new physical model for the amorphous GST (Ge2Sb2Te5) material. Noise intensity is characterized and modelled as a function of bias, temperature and size. Findings from 1/f noise analysis are used to understand the drift mechanism of the amorphous state resistance.
In this paper we present a solar energy harvesting circuit for low-power applications describing circuit architecture and guidelines for an optimal design. We evaluate the performance of two implemented prototypes intended to power a wireless embedded system under different light intensities and different switching frequencies. Measurements show that higher switching frequencies allow reaching the...
In this paper we present two different energy harvesting circuits for solar powered autonomous sensors. Both circuits are able to supply several types of sensor nodes. Performance of these circuits under different light conditions and different loads have been evaluated by experimental results conducted on implemented prototypes. Moreover, starting from the estimated working conditions of the sensor...
We characterize SET operation in Phase Change Memories. A measurement procedure aiming to investigate resistance transition from amorphous to crystalline states is shown. Results give interesting insights on the crystallization process of GST material and a simple model is introduced. Crystallization process obeys to a constant energy law. Fast SET pulses require high power; slow SET pulses can be...
We present here a statistical Monte Carlo (MC) simulator modeling leakage currents across SiO2/high-kappa dielectric stacks. We show that simulations accurately reproduce experimental currents measured at various temperatures on capacitors with different high-k dielectric stacks. We exploit statistical simulations to investigate the impact of high-kappapsilas traps on leakage current distribution...
In this paper, we investigate the feasibility of SiO2/Al2O3 stack tunnel dielectric for future Flash memory generations using statistical leakage current simulations. We show that the statistical Monte Carlo (MC) simulator we employed reproduces accurately leakage currents measured on SiO2/Al2O3 dielectric capacitors. Exploiting its statistical capabilities, we calculate leakage current distributions...
This paper shows that CMOS Class-E PAs are capable of high Power-Added Efficiency (PAE), even when delivering large output powers at Radio Frequency (RF). In particular, a cascode device is used to obtain high efficiency while assuring reliable operation. A differential solution has been adopted to maximize 2nd harmonic suppression and minimize potential on-chip interference. Prototypes realized in...
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