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The following topics are dealt with: ESD; dielectric devices; nanotechnology; NBTI transistor; circuit interconnects; thin film devices; solar cells; low-k-dielectrics; high-k-dielectrics; circuit reliability; memory devices; assembly-and- packaging; failure analysis; MEMS; high voltage device; nanoscale floating body MOSFET; and NBTI induced threshold voltage shift.
For more than 20 years, IC component level ESD requirements have essentially stayed constant, while the silicon technologies rapidly advanced and effective production control methods have vastly improved. The silicon area impact coming from the technology scaling, combined with the high speed circuit performance impact and the influence from the IC package technology advances, are making the ESD design...
A new silicon controlled rectifier low voltage triggered (SCR-LVT), to be adopted as protection structure against electrostatic discharge (ESD) events, has been developed and characterized. A high holding voltage has been obtained thanks to the insertion of two parasitic bipolar transistors, achieved adding a n-buried region to a conventional SCR structure. These two parasitic transistors partially...
NAND flash memories have bit errors that are corrected by error-correction codes (ECC). We present raw error data from multi-level-cell devices from four manufacturers, identify the root-cause mechanisms, and estimate the resulting uncorrectable bit error rates (UBER). Write, retention, and read-disturb errors all contribute. Accurately estimating the UBER requires care in characterization to include...
The ubiquity of threshold voltage relaxation is demonstrated in samples with both conventional and high-k dielectrics following various stress conditions. A technique based on recording short traces of relaxation during each measurement phase of a standard measure-stress-measure sequence allows monitoring and correcting for the otherwise-unknown relaxation component. The properties of relaxation are...
Many recent publications discussing the stress and recovery behavior of bias temperature instability (BTI) have suggested the existence of two components contributing to the phenomenon. One of these components was found to be quickly relaxing while the other was only slowly relaxing or even permanent. Curiously, although the most likely suggested mechanisms are the generation of interface states and...
Nanoelectronic devices based upon self-assembled semiconductor nanowires are excellent research tools for investigating the behavior of structures with sub-lithographic features as well as a promising basis for future information processing technologies. We describe two unique approaches to successfully fabricate nanowire devices, one based upon harvesting and positioning nanowires and one based upon...
Semiconducting and metallic nanocrystals have been embedded in high-k dielectrics for nonvolatile memories for advantages of low leakage currents, large charge storage capacities, and long retention times. However, there are few studies on the reliability issues, such as the breakdown mechanism and relaxation current decay rate. In this paper, authors investigated the reliability of four different...
Advances in process technology enable high volume manufacture of integrated circuits with nano-scale transistor and interconnect technology. This fabrication capability results in the availability of a great range of nano-scale materials and structures such as nano-tubes, thin films, nano-dots, and nanowires. Many of these materials are under consideration as the material for beyond CMOS switches...
In this paper we review some recent results on reliability of MuGFET nanodevices with different gate stacks, including polycrystalline-Si/SiON as well as deposited metal gate/high-k stacks. In the first part we show how we can get information on the interface quality of the sidewall and top interface of the devices, by using an adapted charge pumping technique on gated diode structures. Then we compare...
NBTI is a serious reliability concern in state of the art PMOSFET devices. The implementation of nitrided gate oxides to prevent boron penetration has aggravated the NBTI issue. Because of relaxation effects careful stress and measurement techniques (ldquoOn-the-Flyrdquo) must be used for reliable estimation of device lifetime. This abstract describes a unique enhanced NBTI degradation phenomenon...
A mechanism of DeltaVth variation of NBTI for SRAM load transistor is examined. The variation data is in good agreement with our proposed model. A large fluctuation of NBTI for small size pMOS is not observed in HCI measurement for nMOS, which may be due to the difference of recovery. Two types of equations to get DeltaVth from DeltaIdL by OTF measurement are compared and we have concluded which equation...
Recent negative bias temperature instability (NBTI) studies have come to involve very high electric fields, yet these same studies are used to criticize the lower field ldquoNBTIrdquo models. This study examines both high- and low-field degradation phenomena by monitoring the initial threshold voltage shift (DeltaVTH) as a function of stress time and stress voltage. We demonstrate that the initial...
In recent literature several measurement methods were introduced to characterize the Vth-degradation due to NBTI considering the recovery phenomenon. To our knowledge each method has a severe problem or at least a significant disadvantage. Either there are long delay times, the accuracy is not satisfactory or it is not possible to implement the method with customary equipment. A compromise is to perform...
Mobility degradation due to generation of interface traps (Deltamueff(NIT)) is a well-known phenomenon that has been theoretically interpreted by several mobility models. Based on these analysis, there is a general perception that Deltamueff(NIT) is relatively insignificant (compared to Deltamueff due to ionized impurity) and as such can be safely ignored for performance and reliability analysis....
The reliability of advanced integrated circuit (IC) technologies may be dominated by the interaction of environmental radiation with the devices in the ICs. In particular, single event upsets (SEUs) and soft errors produced by single energetic particles may have a significant impact on the error rate of digital ICs. Additionally, some of the mechanisms responsible for long-term degradation of ICs...
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