Serwis Infona wykorzystuje pliki cookies (ciasteczka). Są to wartości tekstowe, zapamiętywane przez przeglądarkę na urządzeniu użytkownika. Nasz serwis ma dostęp do tych wartości oraz wykorzystuje je do zapamiętania danych dotyczących użytkownika, takich jak np. ustawienia (typu widok ekranu, wybór języka interfejsu), zapamiętanie zalogowania. Korzystanie z serwisu Infona oznacza zgodę na zapis informacji i ich wykorzystanie dla celów korzytania z serwisu. Więcej informacji można znaleźć w Polityce prywatności oraz Regulaminie serwisu. Zamknięcie tego okienka potwierdza zapoznanie się z informacją o plikach cookies, akceptację polityki prywatności i regulaminu oraz sposobu wykorzystywania plików cookies w serwisie. Możesz zmienić ustawienia obsługi cookies w swojej przeglądarce.
Low frequency noise diagnostics is a powerful tool to study the quality of gate stacks and the different interfaces and also gives detailed information on the device performance and reliability. The influence of new materials, different processing treatments and alternative device concepts on the low frequency noise performance will be reviewed for a variety of advanced device technologies including...
We show the impact of process parameters on the electrical performance of complementary Multiple-Gate Tunneling Field Effect Transistors (MuGTFETs), implemented in a MuGFET technology compatible with standard CMOS processing. Firstly, the impact of the gate oxide thickness and implant doping conditions on the tunneling performance is analyzed and compared with TCAD simulations. Secondly, three different...
The multi-gate architecture is considered as a key enabler for further CMOS scaling. FinFETs can readily be manufactured on SOI or bulk substrates. We report for the first time an extensive benchmark of their critical electrical figures of merit. Both alternatives show better scalability than PLANAR CMOS and exhibit similar intrinsic device performance. Introducing SOI substrates and low doped fins...
The multi-gate architecture is considered as a key enabler for further CMOS scaling. FinFETs can readily be manufactured on SOI or bulk substrates. We report for the first time an extensive benchmark of their critical electrical figures of merit. Both alternatives show better scalability than PLANAR CMOS and exhibit similar intrinsic device performance. Introducing SOI substrates and low doped fins...
Despite their excellent control of short channel effects, FinFETs suffer from different trade-offs in the mixed-signal domain, with respect to planar devices. For the first time, we report a complete and comprehensive comparative analysis showing that these trade-offs can be alleviated in advanced FinFET technology. As such, higher voltage gain and transconductance than planar MOSFETs are reached...
In this paper, we investigate the potentialities and properties of HfSiO/MG/cap/TiN gate stack devices, first by identifying the impact of the TiN thickness and its deposition procedure on the device characteristics, and by exploring the use of TaN vs. TiN as the 1st metal layer (MG). Deeper insight into the caps (e.g., Dy) diffusion mechanism is gained by: a) demonstrating stronger diffusion dependence...
While the potential of FinFETs for large-scale integration (LSI) was demonstrated before on relaxed device dimensions, in this paper we present performance data of aggressively scaled transistors, ring oscillators and SRAM cells. FinFET SRAMs are shown to have excellent VDD scalability (SNM=185 mV at 0.6 V), enabling sub-32 nm low-voltage design.
We report, for the first time, a comprehensive study on various capping integration options for WF engineering in MuGFET devices with TiN gate electrode: HfSiO/cap/TiN, cap/HfSiO/TiN and HfSiO/TiN/cap/TiN vs. reference deposition sequence HfSiO/TiN (cap = Al2O3 for pmos, and Dy2O3 or La2O3 for nmos). We show that: 1) low-VT values (Lt 0.3 V) are achieved for both nmos and pmos, with excellent process...
As a result of CMOS scaling, the critical dimension (CD) of integrated circuits has been shrinking. At sub-45 nm nodes, in which FinFET is a viable device architecture, line-edge roughness (LER) in current Si-based technologies forms a significant fraction of the line CD. In such cases, analyzing the impact of LER on FinFET performance is vital for meeting various device specifications. The impact...
Spacer-defined fin-patterning results in double/quadruple fin density and hence is attractive for high performance 32-nm CMOS applications. For the first time 55-nm gate-length FinFET SRAMs with resist- and spacer-defined fins are electrically compared. Due to short-range process variations, SRAM bit-cells with spacer-defined fins show approximately 2.5 times higher variability in static-noise-margin...
Wireless applications require a low power technology that enables digital/analog/RF functions on the same chip. FinFET technology presents a competitive alternative to planar CMOS as it features good digital, analog and low-frequency noise performances. Also, very good matching performance is presented here for the first time. Moreover, FinFETs are shown to be attractive for low-power applications...
In this paper, the suitability of the MUGFET technology as an alternative device architecture for 32 nm CMOS generation is discussed. In particular, the requirements for the MUGFET devices with focus on FIN geometry, gate stack, and junctions are analyzed. Technological challenges related to the processing of MUGFET devices such as, FIN and gate patterning, junctions and spacer formation, are also...
The electro-static discharge robustness of different elevated source drain architectures on a 90 nm CMOS technology is investigated. The study is performed on poly isolated diodes and grounded gate NMOS using transmission line pulse and human body model testing methods. It is found that an improvement up to 45% in ESD robustness can be obtained by the use of elevated source drain process option. Failure...
For a 0.35 μm CMOS technology, an optimized poly buffered LOCOS process is necessary in order to meet the design rules. In this paper, the feasibility of this isolation scheme is demonstrated.
Podaj zakres dat dla filtrowania wyświetlonych wyników. Możesz podać datę początkową, końcową lub obie daty. Daty możesz wpisać ręcznie lub wybrać za pomocą kalendarza.