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A lower power and area efficient VP9 and multi-standard video decoder chip is first-reported for Android 4K TV. It supports prevalent MPEG-x, VP-x, RMx, WMV-x and H.26x series video standards in a single chip. Three high-throughput techniques, look-ahead re-mapping, early stage pipeline and dynamic-scheduled bus translation, are proposed. They cuts the processing times by 51.2% compared to the state-of-the-art...
A 4 K 2 K H.265/HEVC video codec chip supporting 14 video standard formats is implemented on a 1.491.45 mm die in a 28 nm CMOS process. Several HEVC fast algorithms reduce the coding modes by analyzing the content features leading to over 68.5% and 83% of complexity reduction in intra and inter coding, respectively. A fully parallel processing element (PE) array is adopted...
A 4K and Main-10 HEVC video decoder LSI is fabricated in a 28nm CMOS process. It adopts a block-concealed processor (BcP) to improve the visual quality and a bandwidth-suppressed processor (BsP) is newly designed to reduce 30% and 45% of external data accesses in playback and gaming scenario, respectively. It features fully core scalable (FCS) architecture which lowers the required working frequency...
A 4K×2K H.265/HEVC video codec chip is fabricated in a 28nm CMOS process with a core area of 2.16mm2. This LSI chip integrates a dual-standard (H.265 and H.264) video codec and a series of prevalent (VC-1, WMV-7/8/9, VP-6/8, AVS, RM-8/9/10, MPEG-2/4) decoders into a single chip. It contains 3,558K logic gates and 308KB of internal SRAM. Moreover, it simplifies intra/inter-rate-distortion optimization...
A first-reported 4K×2K@60fps digital TV SoC processor supporting 9 video formats and integrating HDMI/MHL receiver is fabricated in a 40nm CMOS process. It adopts error compensation processor (ECP) to improve the visual quality, and designs a memory management unit and resource sharing technique to improve the throughput and area efficiency by 38.5% and 34.3%, respectively. Moreover, a lossless compression...
This paper proposes a digital public address (PA) system which is capable of multi-zone and text-to-speech (TTS) broadcasting functions for campus broadcasting and language listening training/exam. The proposed digital PA system can achieve environmental broadcasting requirement which means different broadcasts for different zones at the same time. On the other hand, it cannot cause noise to other...
a 3D Blu-ray-compliant multimedia processor integrating video decoder, display and graphic engines is presented. To cope with the bandwidth/cost-starved Blu-ray system, this design exploits the time-sharing techniques, leading to 31.3% and 29.1% of area reduction in display and decoder parts. Moreover, a graphic and on-screen-display hardwired handshake effectively reduces the DRAM space by 40%. A...
This paper proposes a novel method of remapping between any amount of individual systems or chips. Any individual system and chip can share a specific address map with other systems over the proposed adaptive memory map switch (AMMS). Because the AMMS is programmable, it allows the dynamic changing on the remapping of target address by setting AMMS. An implemented example is presented here to specify...
Network-on-chip (NoC) has evolved as the promising solution for ever increasing chip level integrations. The architecture of an NoC can be specified by its topology and switching scheme. In this paper, we evaluate these design parameters with exemplified NoC realizations. We adopt popular 2D-mesh and H-star as our topology candidates. The former accompanies with a high-performance iSLIP switch architecture,...
The three-dimensional (3-D) stacking memory is good way to extend the local memory of embedded CPU and/or DSP by the through-silicon-vias (TSVs) technology. In this work, we show a multi-core system with 3-D stacking memory, and the stacking memory can be configured as instruction cache or local data memory for each DSP core. Due to the non-cacheable property of local memory, the programmers have...
A first-reported, sub-mW/fps/view multi-view video decoder chip fully compliant to 3D Blu-ray specifications is reported. It explores the resource sharing so as to integrate not only single-view MPEG-2/VC-1/AVC but multi-view MVC standards into a single die. Moreover, it features pipeline management and clock management units so as to improve the processing throughput and clock power efficiency. A...
In this paper, a power-aware and low power multimedia processor is presented. A novel clock gating scheme and dynamic frequency selection (DFS) are implemented to minimize the power dissipation and it integrates 7-standards (H.264 / VC1 / RV / AVS / MPEG-1 / MPEG-2 / MPEG-4) with several resource-sharing techniques in both algorithmic and architectural levels so as to achieve significant area and...
In this paper, an AVS-embedded multi-format video decoder is presented. It integrates AVS JP@L6.2, H.264 HP@L4.2, VC-1 AP@L3, and MPEG-2 MP@HL in a single chip and features resources sharing, memory management, and early-stage acqusition to facilitate cost and bandwidth efficiency. For the applications of broadcasting, an adaptive error concealment method is proposed. A chip is fabricated and integrates...
The first reported RealVideo-embedded video decoder is presented The embedded streaming (e-Streaming) video decoder integrates RealVideo, MPEG-2, MPEG-4, H.264, and VC-1 by 658 K logic gates and 522 Kbits SRAM. In particular, a RealVideo (RV) is fully-reused and is first integrated into our multi-standard video decoder. It explores RV temporal reference method, RV VLD table reduction, multi-stage...
Due to the local smoothness characteristic of most real-world object surfaces, the per-pixel depth information can be efficiently compressed instead of using an additional color video channel. However, the complexity and hardware requirement are nearly two times higher than coding 2D video. By using sharing-of-motion-information method and analyzing the relationships between texture video and depth...
A Blue-ray Disc (BD) player, back-end SoC supporting multiple protection, video and display formats is fabricated in a 90 nm 1P7M CMOS process with a core area of 62.95 mm2. This SoC adopts a general copy protection (GCP) unit to integrate various kinds of protection algorithms (e.g. AES, CSS, CPPM/CPRM, DES, SHA-1/MD5), designs a dedicated memory management unit (MMU) for realizing multiple video...
A fully-compliant high-definition video decoder LSI for Blu-ray Disc (BD) player is presented. It supports MPEC-2 MP@HL, H.264 HP@L4.1, and VC-1 AP@L3 video decoding in a single chip and features resource sharing and memory management unit to achieve area/throughput efficiency. A test chip is fabricated and integrates 515 K logic gates with 522 Kbits of embedded SRAM in 90nm single-poly seven-metal...
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