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This paper provides a step-by-step guideline for the assessment of an automotive safety microprocessor with ISO 26262 hardware requirements. ISO 26262 part 5 — Product development at the hardware level — specifies the safety activities during the phase of the automotive hardware development. In this phase, hardware safety design is derived (from the results of ISO 26262 part 3 and 4), implemented,...
This paper focuses on micro controller unit (MCU) based platform and field oriented control (FOC) algorithm applying 3rd harmonic injection algorithm. The target application of this paper is power chain systems of electric vehicle (EV) and electric scooter (E-Scooter). The MCU based system on chip (SoC) is proposed, called Bison1, and the proposed platform is called Bison1 platform which is including...
This paper proposes a novel method of remapping between any amount of individual systems or chips. Any individual system and chip can share a specific address map with other systems over the proposed adaptive memory map switch (AMMS). Because the AMMS is programmable, it allows the dynamic changing on the remapping of target address by setting AMMS. An implemented example is presented here to specify...
This paper presents an on-line error detection and correction techniques for through silicon via (TSV) in three-dimensional integrated circuit (3-D IC). The proposed architecture is based on biresidue codes to detect and correct the error on-line in the failed TSV over syndrome analysis. Experimental results show the proposed design has good performance in area and TSV overhead and improves the yield...
Power consumption is a critical problem for very large scale integration (VLSI) systems, especially in deep-sub micro systems. Due to the systems are more and more complex, the power issue is a challenge for IC (integrated circuits) design. Hence, this paper develops a hybrid low power technology (HLPT) to deal with the different complexity applications. Additionally, the proposed HLPT is from system-level...
In this work, we propose an electronic system-level (ESL) power estimation framework which can support several low power methodologies such as dynamic voltage and frequency scaling (DVFS) and dynamic power management (DPM). Based on the proposed framework, designers can analyze the system power and develop the suitable low power strategies for different applications in the early design stage. The...
A low power and full ASIC MPEG-2/4 AAC single chip decoder is presented. The decoding blocks are partitioned into four dedicated hardware modules with the complexity and operational type analysis. Through algorithm, architecture, RTL and circuit level lower power techniques, the proposed AAC decoder is operated at 1.4 MHz for the 44.1 KHz sampling frequency and consumes only 0.21 mW using TSMC 0.13...
In complex SoC design, the reusable IP is very useful to achieve the whole system with high verification. Based on this issue, a hardware and software (HW/SW) co-design approach can obtain maximum performance, and is easily integrated with the other functions to complete the system. This paper presents the multi-standard audio decoder design with hardware/software co-design flow. First we need to...
From system-on-chip (SOC) perspective, memory bandwidth plays an important role in system performance for video coding applications. Owing to the locality of video data, the data reuse scheme is widely applied to reduce the memory bandwidth requirement. For further improvement of performance, frame-based data reuse scheme, single reference frame and multiple current macroblocks (SRMC), can provide...
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