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A liquid crystal (LC) cell made of silicon (Si) electrodes was fabricated to achieve self-routing of optical signals. As optical pulses (1.06 μm wavelength) passed through the cell, they excited free carriers in the Si electrode, which triggered the voltage application to the LC layer. Consequently, the polarization direction of the succeeding pulses became perpendicular to that of the preceding pulses,...
We have investigated the effects of irradiation on space solar cell degradation characteristic. We examined the effects of beam conditions such as fluence rate and beam expansion method. For the fluence rate experiment, in the case of proton irradiations, the degradation did not depend on fluence rate. Meanwhile, in the case of electron irradiation, Si cell results showed degradation dependent on...
According to ITRS2009, the detection of 18nm particles is required for 2010, but the latest laser scattering wafer inspection system is not capable of detecting particles smaller than 28 nm. Therefore, it is necessary to establish the method of detecting smaller particles. We developed a method to detect particles that are below the detection limit of the particle detection system by depositing SiO...
We comparatively investigated the impact of layout and trench on four types of field oxide Pch MOSTs in a thick film SOI technology with due consideration to isolation trench. High blocking capability (~20 V per um of drift length) for both off- and on- state breakdown voltage close to 300 V, along with reasonable high temperature reverse bias ruggedness, has been experimentally realized with minimum...
An optical gate was fabricated with silicon, liquid crystal, and a polarizer. Photons excited free carriers in silicon, which triggered voltage application to the cell. Consequently, optical signals opened or closed their path by themselves.
Advanced large scale integrated circuits (LSI) and smart sensor systems require nanoscale interconnection to transmit signals. In this work, an approach to realize multilayer interconnection based on ultraviolet nanoimprint lithography (UV-NIL) technology and copper electroplating is discussed. UV-NIL is a low-cost, mass-production technology. Nanoscale dot array patterns and line array patterns of...
We demonstrated 40nm gate length "gate overlapped raised extension structure: GORES MOSFET" without halo implantation and prove that the ultra shallow junction (USJ) could coexist with the reducing parasitic resistance in GORES MOSFET. It is the new concept planar transistor with the gate overlapping the in-situ doped epitaxial extension to break through the trade off relation between reducing...
Shallower junctions must be formed to make transistors work for the 32-nm node. Many kinds of technologies, such as co-implantation, laser spike annealing (LSA), and flash lamp annealing, have been energetically studied to form ultra-shallow junctions. We focused on in-situ doped selective Si epitaxy, with which the short channel effect and the parasitic resistance can be made compatible. Using this...
A raised source/drain extension (RSDE) pFET on (110) Si wafer is demonstrated for the first time with in-situ doped selective epitaxy technology. Roll-off has been effectively improved, resulting from the elimination of ion channeling in (110) Si. Due to the hole mobility enhancement and parasitic resistance reduction, ion of 389muA/mum (Vd= -1.0 V) has been achieved at Lmin around 30nm extracted...
We propose HfSix/HfO2 gate stacks as the most suitable combination for high performance nMOSFETs. An equivalent work function (WF) to n+poly-Si was obtained by controlling Hf/Si ratio of the electrode. The highest electron mobility ever reported was achieved in the thinner Tinv region down to 1.6 nm by low temperature process without using plasma nitridation both for metal and high-k fabrication....
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