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Proportional fairness in the downlink of a single-cell multi-carrier code-division-multiple-access (MC-CDMA) network in the presence of a jammer is considered in this paper. We assume the jammer can find the spreading sequences of the base station (BS) and use them in causing interference on all available channels to reduce the sum rate of the BS to users to the extent possible. Besides, we require...
This paper presents a novel coupled-oscillator RFIC for multi-phase clock generation. The design achieves low phase noise while maintaining strong coupling among oscillator cores. The proposed transformer-based dual-tank topology forms a loop of coupling path for enhanced multi-phase coupling. The phase noise optimization is accomplished by leveraging the dual-tank and the adaptive-biasing feedback...
Neural stem cells are self-renewing, multipotent cells that can be found in subventricular (SVZ) and subgranular (SGZ) zones of the brain. These zones are susceptible to irradiation-induced apoptosis and oxidative stress. Melatonin (MLT) is a natural protector of neural cells against toxicity. The aim of this study was to evaluate the effects of MLT as a radio-protective material effective in reducing...
This paper presents the design of a 6-path offset based feedforward amplifier with high linearity. It leads to both high order nonlinearity compensation and 1dB compression point (P1dB) expansion at the same time. The structure avoids the use of extra gain stages and the superposition mechanism improves the gain which saves the power. The linearized amplifier was implemented by the 130nm SiGe technology...
This paper presents a novel 8.8 GHz voltage-controlled oscillator (V CO), which employs a dual-tank structure and the impulse sensitivity function (ISF) manipulation technique. By utilizing these techniques, the behavior of both the tail and the cross-coupled transistors is optimized compared to the conventional VCO; therefore, the noise from the transistors and the low quality of tank is reduced;...
This paper presents a multi-phase clock generation technique, which employs coupled oscillators with capacitive-coupling to achieve both low-power and low-noise characteristics. An oscillator core equipped with both dual tanks and adaptive biasing feedback is proposed. To prove the concept, a four-core coupled oscillator is fabricated in a 130nm CMOS RF SOI process. The VCO RFIC achieves measured...
A 1.8–2.2 GHz CMOS LNA featuring a record 0.8dB noise figure is reported using an inductively-degenerated cascode topology combined with floating-body transistors and high-Q passives on an SOI substrate. The LNA achieves 11 dB of power gain while consuming 6.6 mW dc power from a 1.5V supply. The LNA covers Bands 1, 2, and 3 of 3GPP, and is suitable for LTE terminal applications. IIP3 of +4.6dBm and...
An often-overlooked but important CMOS device sizing approach that significantly affects circuit noise performance has been discussed theoretically and verified by simulation. It has been demonstrated that sizing a CMOS device using maximum number of gate fingers results in as much as 9dB improvement in circuit noise figure. Furthermore, and as side benefits, parasitic capacitance, linearity, and...
Noise cancelation characteristic of Capacitive Cross-Coupling (CCC) and Cross-Coupled Transistor Pair (CCTP) circuit configurations to remedy noise degradation caused by active Q-Enhancement Circuit is analyzed theoretically and demonstrated via simulation. Differential common-gate low-noise amplifier (LNA) has been utilized as the reference circuit for this work. The simulation has been carried out...
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