An often-overlooked but important CMOS device sizing approach that significantly affects circuit noise performance has been discussed theoretically and verified by simulation. It has been demonstrated that sizing a CMOS device using maximum number of gate fingers results in as much as 9dB improvement in circuit noise figure. Furthermore, and as side benefits, parasitic capacitance, linearity, and power consumption are also improved considerably. For the purpose of simulation, Common-Gate Low-Noise Amplifier (LNA) has been utilized as the reference circuit. The simulation has been carried out using 0.12µm CMOS process.