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In a context of the end of Moore's law, energy dissipation constitutes a real challenge. Among the new energy efficient paradigms for data processing, bio-inspired computing is very promising, moreover introducing cognitive characteristics. As applications at very high scale are addressed, the size and energy dissipation of both the neuron and synapse cells needs to be minimized. In this context,...
A novel training technique for digital predistortion (DPD) systems is presented. Previous techniques rely on the time-domain (TD) difference between the ideal transmitter input and the distorted amplifier output as an error metric. This work presents DPD training based solely on frequency-domain signal-to-distortion-ratio (SDR) information. The only a priori information required is the spectral occupancy...
A linearization technique for bipolar amplifiers based on Derivative Superposition is presented. The proposed technique provides excellent linearity, while having low sensitivity on the bias conditions. A demonstrator circuit, along with a reference circuit using out-of-band linearization for linearity comparison, have been designed and implemented in a 0:25μm SiGe:C BiCMOS technology to show the...
The operation of SiGe HBTs at cryogenic temperatures is investigated experimentally and theoretically. It is demonstrated that the collector current at cryogenic temperatures is caused by electron tunneling through the base. The temperature dependence of the transistor characteristics reveals a transition from conventional thermally activated transport at room temperature to tunneling dominated transport...
Radio-Frequency (RF) losses on High-Resistivity Silicon (HRS) substrates were studied for several different surface passivation layers comprising thin-films of SiC, SiN and SiO2 In many combinations, losses from conductive surface channels were reduced and increasing the number of interfaces between thin-films was found to be beneficial. In some cases the surface losses were completely eliminated...
CMOS electronics constitutes the backbone of our information society. The extraordinary success of CMOS is based on the unique scaling properties of the Si MOSFET. Over the last decade, increasing concerns have been expressed about the ability of the Si MOSFET to continue its historical scaling path. This threatens the future of Moore's Law and its trifecta of benefits: cost, power and performance...
It is envisioned that future 5G wireless links will extensively employ multiple mm-Wave spectra (e.g., 28GHz, 37GHz, 39GHz, and 70GHz). A major bottom neck for silicon-based mm-Wave electronics lies in the generation of mm-Wave signals with high energy efficiency, high linearity, and large modulation bandwidth, all of which are indispensable to support Gbit/s complex modulations with large peak-to-average-power...
A multimode 5–6 GHz SiGe BiCMOS PA IC that powers the emerging Wireless LAN applications is presented. The design can be realized in a 1.35 × 0.7 active area as a standalone power amplifier (PA) or the transmit (Tx) chain of a Front-end IC. The design features multiple modes with low DEVM supporting 1024 QAM data rates and >20 dB accurate power controls. The linearity is well scaled with supply...
Achieving a wideband, efficient, scalable and low-cost interface between IC and antennas is critical for mm-wave transceivers in silicon. This paper presents an antenna-IC co-integration approach to achieve dual-polarization transmission and reception using on-chip dual-pol feeds that aperture-couple through a slot in the on-chip ground to a patch antenna on the back side of the IC. The proposed wafer-scale...
A novel balanced reflect-type vector modulator topology is presented. The use of only four 90° hybrid couplers allows a much-reduced area, competitive with active solutions, while keeping all benefits of the passive topology. A test circuit was developed using a 0.25 μm SiGe BiCMOS technology. The K-band vector modulator occupies 353 × 435 μm and measurements showed a very well centered and uniformly...
A monolithically integrated C-band receiver is used to demonstrate the potential of an advanced photonic BiCMOS process. We show that the particular SiGe HBTs integrated in this process strongly improve the receiver's frequency response, BER and noise behavior, compared to the same circuit fabricated in a previous process generation featuring slower transistors.
This paper presents an RF-MEMS switch fabricated in a 0.13 μm SiGe BiCMOS process technology for 240 GHz applications. The fabricated RF-MEMS switch provides a high capacitance Con/Coff ratio of 8.78 and beyond state of the art RF performances, 0.44 dB of insertion loss and 24.6 dB of isolation at 240 GHz. The return loss is better than 9.6 dB over the J-band (220–325 GHz). To the best of the authors'...
This paper deals with the reduction of the process thermal budget in a 55-nm BiCMOS technology for improving SiGe HBTs transit frequency, fT. Since MOSFETs are directly impacted by this modification, process adjustments are implemented to recover performances and parametric yield. Spike annealing temperature reduction, thermal re-oxidation replacement and Dynamic Surface Annealing implementation are...
This paper presents three different technology modules, integrated into a 0.13-μm SiGe BiCMOS process; namely RF-MEMS switch, microfluidics and heterogeneous integration technologies. The RF-MEMS switch module is optimized for mm-wave applications and offers superior performance figures at D-band with a wafer level encapsulated packaging option. The microfluidics module which is embedded by bonding...
In this paper, we discuss architectures and integrated circuits for efficient, reconfigurable and compact millimeter-wave beamforming in silicon. First, we present techniques to improve peak and back-off power-added efficiency (PAE) of SiGe power amplifiers, demonstrated with a 28-GHz harmonic-tuned amplifier (+15.5 dBm output 1-dB compression point, 35% peak PAE, 11.5% PAE at 6-dB back-off) and a...
This paper presents a 28–32 GHz transceiver chip architecture in SiGe BiCMOS to meet the requirements of 5G phased-array communication links. An asymmetric design is employed for the transmit and receive paths to deliver an output P1dB of 8 dBm in TX mode and to achieve an input P1dB of 0 dBm in RX mode. The chip can operate with an external LO at 10–16 GHz and 20–28 GHz with the use of an on-chip...
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