This paper presents a multi-phase clock generation technique, which employs coupled oscillators with capacitive-coupling to achieve both low-power and low-noise characteristics. An oscillator core equipped with both dual tanks and adaptive biasing feedback is proposed. To prove the concept, a four-core coupled oscillator is fabricated in a 130nm CMOS RF SOI process. The VCO RFIC achieves measured phase noise of −133 dBc/Hz @ 1MHz offset from the 2.33 GHz operating frequency. The current consumption for each oscillator core is 10 mA from a 1V supply voltage. The Figure of Merit (FoM) of the 8-phase VCO circuit is 184.4 dBc/Hz while it is 193.3 dBc/Hz per phase.