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Introduction of a dual beam (DB) millisecond (mSec) or nanosecond (nSec laser annealing in contact module results in a drastic reduction of contact resistivity. Dependence of this benefit on laser annealing parameters is detailed. The annealing power/temperature condition needed for initiating solid or liquid phase epitaxy (SPE, LPE defines a lower process boundary, while impact of laser annealing...
Nanosecond (nsec) melt annealing offers unique capabilities such as ultra low thermal budget, high dopant activation and super abruption junctions. But process integration is more difficult than millisecond (msec) annealing due to two orders of magnitude smaller heat diffusion length. In this paper, we will discuss some of the key challenges, and propose a new approach that combines the benefits of...
Evolution of CMOS technology has created new opportunities for millisecond annealing beyond the traditional dopant activation and junction formation. Strain enhancement, gate stack property modifications, silicide formation, and contact interface engineering are a few examples. In this paper, we review various applications of millisecond annealing for advanced logic device fabrications. Extendibility...
We investigate the use of sub-millisecond laser spike annealing (LSA) for two applications: n-type germanium shallow junction activation and titanium silicide formation. For Ge junction, impact of various process parameters including dwell times, peak annealing and substrate temperatures are evaluated. Arsenic dopant activation level of ~1e20 cm−3 is obtained. It is shown that short dwell time is...
N-type dopant activation by long dwell laser spike annealing, and subsequent deactivation during furnace annealing, has been studied using Hall measurements. Carrier activation is improved as the dwell time is increased from 10 to 20ms. For high concentration P junctions, deactivation is observed at temperatures as low as 400°C. However, activation can be fully recovered by a second LSA anneal suggesting...
Recent work has shown that laser annealing may have advantages over conventional RTP for nickel silicidation formation, such as lower leakage and better device performance [1, 2]. However, there are a number of requirements that must be met by any millisecond annealing tool to successfully bring this process to a high volume manufacturing environment. Ultratech's new low-temperature LSA system is...
Recently we reported the development of new dual beam laser spike annealing system that offers flexible temperature profiles and a broad range of process parameters. For example, the dwell time can be varied from a few hundred microseconds to several tens of milliseconds, while simultaneously allowing the substrate temperature to be lowered significantly to accommodate silicide processes. Short anneal...
A new dual-beam laser spike annealing (DB-LSA) technology is developed to expand the application space of non-melt laser annealing. In the standard LSA configuration, a single narrow laser beam is used to heat the wafer surface from substrate temperature to the peak annealing temperature close to silicon melt. In DB-LSA, a second wide laser beam is incorporated to preheat the wafer. The dual beam...
LSA was first introduced into mainstream semiconductor manufacturing for logic IC's at the 65 nm node, continuing the natural evolution of semiconductor thermal processing to higher temperatures (>1200??C) and shorter times (100's of microseconds). The initial application was a simple one-step LSA to assist spike-RTA in dopant activation of the source/drain and polysilicon gate regions. Since then,...
Laser spike annealing (LSA) is a disruptive technology which has been successfully demonstrated for advanced junction engineering—creating highly activated ultra-shallow junctions with near diffusion-less boundaries. These produce higher performing devices with improved drive currents and/or lower leakage currents, and provide design engineers more opportunities for product enhancements. LSA has become...
Strain engineering has become a workhorse in increasing charge carrier mobility to boost performance for sub-45nm CMOS logic technologies. While pFET transistors with embedded Si1−xGex layers in the S/D region have been widely employed to induce compressive strain in the silicon channel, nFET transistors have mostly depended on either tensile liners or stress memorization techniques (SMT) to introduce...
The introduction of new materials in recent years puts more stringent requirements on thermal budget management. For example, high Ge concentration in e-SiGe used for strain engineering makes wafers prone to thermal plastic deformation which limits the maximum annealing temperature. In this paper, we will explore ways to expand the process window using sub-millisecond laser spike annealing. Focus...
Scaling of source/drain extension junctions continues to be a major focus for sub 45 nm planar CMOS process development. Device scalability, drive current, and leakage performance are determined by junction depth, activation, and residual disorder. These requirements have driven ion implants into the deep sub-keV regime and integration of millisecond anneals for activation. In this paper, we introduce...
Sub-melt millisecond annealing technologies have been widely accepted for current and future IC fabrication. Real-time temperature control, both within wafer and from wafer-to-wafer, is one of the key challenges that must be addressed for the successful introduction of any millisecond annealing technology into a production environment. In this paper, we show results from a novel pyrometry approach...
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