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With the rapid increase in the number of new product introductions, the volume & complexity of manufacturing changes has the potential to overwhelm the development, quality, coordination, and delivery of equipment training, which, in turn, could result in delays in these new product introductions. This abstract describes how an application of a Lean Manufacturing principle averted this risk and...
In this paper we present characterization, analysis, and methodology for the reduction of surface impurities trapped in the silicon layers at the onset of epitaxial growth. In CVD silicon technology, wet and dry clean of the silicon surface are used to remove native oxide from the surface. However, there are still residual impurities that require desorption via thermal baking to provide a clean interface...
We present a low cost optical macro inspection system for the wafer edge. The system is able to inspect the full wafer edge (front-, backside and apex) and provides a short feedback loop to the unit processes. Furthermore the use of image processing methods enables inspection without additional time loss. This inspection system can be installed on all wafer rotating tools with free space for hardware...
Accelerated design rule (DR) shrinkage is introducing new challenges to the world of process control, yield monitoring and wafer inspection (WI). One of the main challenges of WI is the detection of small defects below the optical resolution limit of the inspection systems. This paper present a new optical scheme for inspection of advanced SRAM patterns and demonstrates the significant value of the...
This CMP processes are generally well known and established critical steps in semiconductor manufacturing, but must be very closely monitored and controlled to maintain process uniformity and minimize process induced defects. CMP processes are generally monitored using a combination of blanket test wafers, short loop patterned wafers and product wafers, along with a variety of in-situ controls. This...
A new technique in qualification of low temperature nickel silicide process is studied. Bare silicon wafers are first oxidized to form a thick film of thermal oxide, followed by nickel and titanium film stack deposition. The samples are then annealed at low temperature using a rapid thermal processing tool. It is shown that the nickel and titanium film stack forms an alloy above the thermal oxide...
Rotary chemical-mechanical polishing (CMP) tools are widely used for integrated circuit (IC) manufacture. Logic device manufacturing has required CMP for front end (FEOL) and back end (BEOL) processes, such as shallow trench isolation (STI), high-K metal gate (HKMG), dielectric (PMD, ILD, Contact), and interconnect metallization (Cu). Recently, manufacturers of memory ICs adopted Cu metallization...
The main objective of this study was to identify if there is any change in wafer warpage after bevel clean process, which might lead to higher film stress at device area in further processes. Correlation between bevel film Etch Rate (ER) and wafer warpage was also investigated. 25 kA thermal oxides (Tox) were etched on back side with various thicknesses remaining to generate a different amount of...
The lithography cell is widely accepted as the most challenging area of a fab to manage cost effectively. Reticle coordination, re-entrant flows and frequent set-up changes create bottlenecks in the Litho module. There is a strong need to use optimization to better match lots and tools, keeping litho tools fully utilized and reducing wafer cycle time. A new solution, called Applied SmartSched™, for...
Photolithography has been one of the primary processes driving semiconductor advances for the past few decades. In order to make faster, more reliable devices, designers drive circuit scaling to its limits. Equipment and material suppliers must create products to meet the throughput and lithographic performance standards required of advanced devices. Track equipment performance and process architecture...
Product test results deliver multiple data about yield and detractors, comprising their centering and dispersions. They present a challenge for information delivery, in particular when the data ranges imply more than 3 orders of magnitude. To visualize them in a “at-a-glance” or “one-shot” dashboard, we present Yp and Ypk as a practical solution. This set of indicators Yp and Ypk is calculated relative...
Elements of a yield model combining multiple input metrics will be reviewed. This model has been applied to multiple products across 65nm and 45nm SOI technology nodes. It provides long term yield metrics as well as yield diagnostics. Focus will be on the addition of After Develop Inspection (ADI) yield metrics into an existing framework which incorporates high resolution defect scans (PLY) and scribe...
In this paper we present an early detection mechanism for semiconductor circuit yield prediction and tracking. Several discrete devices used as components of functional circuits have been examined by their first-metal level test data and correlated to the higher metal level functional yield. A concept of Device Health Composite Yield is also introduced in this paper.
In this work, we report on ZrO2 position effect of ALD HfZrOx gate dielectric with a La2O3 capping layer for gate-first flow. The basic electrical characteristics of devices were compared with different ZrO2 position in HfZrOx dielectric. Experimental results show : (1) Under top La2O3 capping layer for n-type Metal-Oxide-Silicon capacitor (nMOSCAP) device, ZrO2 position on both of top and bottom...
The semiconductor industry experienced increased requirements during the period 2008–2010. These requirements were followed by more wafer starts (loading upside). Micron Israel's 200mm factory capacity increased by more than 40% within one year. The automated material handling system (AMHS) was not originally intended to support a 40% load increase. Prior to the load increase, the 200mm AMHS was not...
This paper identifies post etch killer defects, e.g., core bridging, small particle and tiny bridging, and investigates the possible solutions in a SADP module. Among the killer defect adders, core bridging and small particle are commonly observed after the oxide core removal by BOE. Core bridging adder is a carbon-containing polymeric by-product during nitride spacer open; by introducing additional...
A recently developed precursor, AbaCus, has been evaluated for use in ultra-low temperature copper deposition by PEALD. Film adhesion, platability and process window evaluation demonstrate a strong capability of this precursor to overcome current metallization challenges.
As development phases became shorter, fast defect characterization is highly important. In addition, new chemicals involved in sub 28nm semiconductor processes introduce new types of defects. The variety of defect types complicates defect root cause analysis, so that image based defect analysis is limited, and defect material information becomes more important. Thus elemental analysis of defects in...
With every new manufacturing node also come new modes of failures. Being able to identify these new fail modes and solve them quickly is the key to bring a manufacturing process to mass production readiness. Inline inspection is typically used for studying defects at critical layers. However, this is often limited by the amount of defects that can be visually inspected and to be able to qualify them...
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