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We have evaluated the impact on the reliability of an innovative process flow, specifically designed for peripheral MOSFETs of DRAM memories. Al and MgO layers are deposited, diffused into the gate stacks of NMOS and PMOS and finally removed. We have demonstrated an anomalous yet predictable PBTI behavior, coupled with a more standard NBTI one. Decent lifetime is achieved for both gate stacks, demonstrating...
Deep insights into the Off-State Stress (OSS) degradation mechanism on p-MOSFETs with High-K/Metal Gate technology are presented in this paper. Large subthreshold slope degradation, or positive Vth shift is observed in high, or low Vth devices, where both phenomena impact the off current degradation. The OSS degradation mechanism in pMOS is generated by (1) hot carrier generation close to the drain...
This paper analyzes the amplitude of Random Telegraph Noise (RTN) caused by a single trap in the silicon film of UTBOX devices by two-dimensional (2-D) numerical simulations. The dependence of the relative RTN amplitude on the bias condition and trap position is simulated, explaining the large variability of the RTN amplitude. The simulated traps close to the source or drain have an asymmetric VD...
This paper investigates the silicon film thickness influence on extensionless Ultra Thin Body and Buried Oxide (UTBB) FDSOI devices applied in a dynamic threshold voltage (DT2) operation (VB=VG) over the conventional one (VB=0V). A 6nm silicon thickness in enhanced DT (eDT), where the back gate bias is a multiple value of the front gate one (VB=k×VG), was also considered and compared to the other...
In this work we have investigated the impact of Off State Stress (OSS) on nMOSFETs in High-K/Metal Gate (HKMG) technology. Although in standard poly-SiO2/SiON devices the impact of OSS is relatively limited and causes an increase in VTH, in the case of HKMG larger degradation is observed, with negative VTH shift. A significant increase of the device Off state leakage is observed, causing a serious...
In this work, we investigate the thermal stability and NBTI reliability of Si1−xGex channel devices for DRAM applications for the first time. The results show that Si1−xGex channel devices have improved NBTI robustness compared to Si channel devices in DRAM peripheral transistors. It is demonstrated that the Si1−xGex channel devices with Si cap layer do not exhibit degraded electrical characteristics...
This paper analyzes the read windows of decananometer UTBOX SOI 1T-DRAM memory devices focusing on the mechanisms involved as a function of the applied gate voltage during the read operation. It will be demonstrated both experimentally and by simulation that a novel two-sided read window is possible where the two main effects present, GIDL and parasitic BJT, can be effectively accounted for in two...
This paper aims to analyze the band gap and the pulsed back gate bias influence on the retention time of an UTBOX SOI applied as a 1T-DRAM memory cell. This parameter is increased for higher band gap and constant whatever the pulsed back gate level during the write state. No significant difference on the retention time was observed when comparing the pulsed and constant back gate bias.
The Low-Frequency (LF) noise in Bulk and DTMOS triple-gate FinFETs is experimentally investigated under 60 MeV proton irradiation. Moreover, the important figures of merit for the analog performance such as Early voltage and intrinsic voltage gain will be analyzed. The results indicate that the better electrical characteristics and analog performance of DTMOS FinFETs make them very competitive candidates...
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