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This letter reports on the spike anneal temperature influence on the retention time of 1T-dynamic random access memory cells using a single silicon-on-insulator transistor on ultrathin buried oxide wafers. A 20$^{\circ}{\rm C}$ temperature difference (from 1070$^{\circ}{\rm C}$ to 1050$^{\circ}{\rm C}$ ) in the peak process temperature during the spike anneal after the source/drain implantation...
This paper analyzes the read windows of decananometer UTBOX SOI 1T-DRAM memory devices focusing on the mechanisms involved as a function of the applied gate voltage during the read operation. It will be demonstrated both experimentally and by simulation that a novel two-sided read window is possible where the two main effects present, GIDL and parasitic BJT, can be effectively accounted for in two...
This paper aims to analyze the band gap and the pulsed back gate bias influence on the retention time of an UTBOX SOI applied as a 1T-DRAM memory cell. This parameter is increased for higher band gap and constant whatever the pulsed back gate level during the write state. No significant difference on the retention time was observed when comparing the pulsed and constant back gate bias.
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