The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Two 23 GHz low-noise amplifier (LNA) have been designed and implemented by 45 nm planar bulk-CMOS technology with high-Q above-IC inductors. In the designed LNAs, the structure of cascode amplifier with source inductive degeneration is used. All high-Q above-IC inductors have been implemented by thin-film wafer-level packaging (WLP) technology. The fabricated one-stage LNA has a good linearity where...
The purpose of the article is to present the integration of embedded dies and passives components both being integrated on a high resistivity silicon (HRSi) substrate. Integrated dies are thinned down to a 17 mum thickness and embedded with their associated passives.
A 23 GHz electrostatic discharge-protected low-noise amplifier (LNA) has been designed and implemented by 45 nm planar bulk-CMOS technology with high-Q above-IC inductors. In the designed LNA, the structure of a one-stage cascode amplifier with source inductive degeneration is used. All high-Q above-IC inductors have been implemented by thin-film wafer-level packaging technology. The fabricated LNA...
Modern commercial telecommunication devices tend to integrate more and more functionality on a single chip, the so called SoC (System on a Chip) approach. This results in ultra-compact and low cost realization. However antenna filters and diplexer are still important parts in the transmit/receive chain for which until now no on-chip solution is possible that meets the requirements. In this work we...
This paper demonstrates a broadband LNA for 60-GHz WPAN and a 92-GHz low-power distributed amplifier (DA) in an advanced CMOS technology. A post-processed technology (above-IC), used for packaging and bonding pads redistribution, provides ultra-low-loss on-chip passives in a cost-effective solution. In the WPAN bandwidth (57-64 GHz), the LNA has a 13.4 dB peak gain, a NF between 5.6-6.7 dB and a gain...
3D thin-film technology including substrate vias and integrated passives is used as a platform for heterogeneous integration of high frequency wireless systems and radar. The features of the technology are first described and next demonstrated with an integrated Doppler radar operating in the Ku band.
Scaling of CMOS transistors beyond 45 nm requires architectural redesign of the devices. FinFETs are proposed to recover the reduced channel control. This work evaluates the perspective of RF design in planar bulk vs. FinFET SOI for (sub-)45 nm CMOS on a key RF circuit: a low-noise amplifier (LNA). The planar and FinFET devices with channel lengths down to 40 nm are compared in both wideband and narrowband...
In this paper we present the integration of high-quality passive components and circuits within a thin-film technology on high-resistivity silicon. 100 mum thick wafers are used, allowing the integration of though-silicon vias with a diameter of 100 mum and the implementation of high-quality passive components in a microstrip configuration. Integrated high-density capacitors (650 pF/mm2), resistors...
A 4.7-to-6.4 GHz VCO is designed in 45 nm bulk CMOS using an above-IC inductor on top of the active circuitry, yielding 28% area reduction. The inductor is shielded from the circuitry, using the top metal layers of the CMOS back- end, which enables the proposed 3D integration for low-cost performance extension. The fully integrated VCO consumes just 400 muW, achieves a FoM of 185 dB, and occupies...
With the increasing cost of scaled CMOS, effort is spent in maximizing performance attainable in already available technologies. Above-IC technology (A-IC), consisting of a 5mum thick electroplated Cu layer on an 18mum low-K BCB dielectric, post-processed on top of the CMOS, provides a low-cost solution to achieve high-Q passive devices, with relaxed mask requirements. A technique is presented to...
Millimeter-wave commercial communication systems are getting a lot of attention in the recent years, and therefore there is a need of implementing miniaturized high-quality passive components at these frequencies. In this paper, we demonstrate the integration of ultra-miniaturized cavities on the thin-film multi-chip module technology (MCM-D) by using through-substrate vias on 100 mum thick high-resistivity...
The integration of through-substrate vias on 100 mum thick high-resistivity silicon (HRSi) wafers within the thin-film multi-chip module technology (MCM-D) is demonstrated in this paper. High quality integrated lumped elements such as thin-film resistors, capacitors and inductors are demonstrated on a microstrip configuration within an MCM-D technology. Microstrip lines integrated on the thin HRSi...
The integration of through-substrate vias on 100 mum thick high-resistivity silicon (HRSi) wafers within the thin-film multi-chip module technology (MCM-D) is demonstrated in this paper. High quality integrated lumped elements such as thin-film resistors, capacitors and inductors are demonstrated on a microstrip configuration within an MCM-D technology. Microstrip lines integrated on the thin HRSi...
This work presents a fully integrated differential 5.8 GHz low-noise amplifier (LNA). The LNA is fabricated in a 90 nm RF-CMOS process and has a power gain of 12.5 dB, an IIP3 of 4dBm, and a noise figure of 1.7 dB consuming 14 mA from a 1.2 V supply. Compared to previously reported differential CMOS designs this LNA show lower noise figure and better linearity.
Serial links are an effective solution to address the growing on-chip communication bottlenecks in nano-CMOS technologies. This paper proposes efficient link architecture for on-chip serial links and networks. The proposed solution consists of a pre-emphasized differential driver and receiver interconnected by LC transmission lines. The LC transmission lines are implemented in packaging layers post...
A systematic implementation of ESD protection for a 17 GHz LNA in 130 nm SiGeC BiCMOS technology is presented. The ability to achieve pre-silicon ESD reliability confidence is demonstrated through the comparison of HBM ESD simulations and measurements on the circuit. The inductor-based ESD protection methodology achieves more than 6 kV HBM ESD robustness for the LNA, the highest ever reported in a...
A QSA airgap isolated HBT module, embedded in a 0.13mum BiCMOS technology, reaches fT/fmaxvalues of 205/275GHz and a 3.5ps CML gate-delay. A 17GHz LNA using high quality passives sustains above 8kV HBM ESD stress
In the past years, the RF-MEMS activities have focused on the development of generic technology platforms integrating switches as well as tunable and fixed passives components. This is in strict opposition to a former device-centered development of the RF-MEMS technologies. Fruitful efforts were put at IMEC in the reliability analysis and modeling of the devices, the exploration of various packaging...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.