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A method for on-chip extraction of random telegraph noise (RTN) parameters from transistors is proposed. Exploiting the nature of exponential distributed RTN events, the proposed circuit enables the automatic extraction of mean RTN time constants from a large array of small-area transistors. The on-chip data processing provides a simplified measurement infrastructure, reduces the measurement time...
This paper describes a 28nm fully integrated 79 GHz Phase Modulated radar SoC including 2TX, 2RX and the mm-wave frequency generation. A custom digital core generates the pseudo random sequence and performs correlation and accumulation of the digitized received data. With 1W power consumption, 7.5 cm range resolution is achieved while antennas arrangement allows for 5° resolution over ±60° elevation...
The paper presents a subsampling PLL which uses a 10-bit, 0.5 ps unit step Digital-to-Time Converter (DTC) in the phase-error comparison path for the fractional-N lock. The gain and nonlinearity of the DTC can be digitally calibrated in the background while the PLL operates normally. During fractional multiplication of a 40 MHz reference to frequencies around 10 GHz, the measured jitter is in the...
Vertical nanowire logic circuits may enable device density scaling well beyond lateral CMOS layouts limited by gate and contact placement. In this paper, we compared the performance, layout efficiency, SRAM design, and parasitics between vertical (VFETs) gate-all-around (GAA) transistors with lateral (LFETs) targeting 5nm. We reviewed some of the unique considerations of VFET device and circuit influences.
This paper presents a concept of a tunable inductance using coupled transmission lines. The proposed method suggests applying signal at one line of a shorted coupled transmission line and injecting current at the other line of the coupled pair. This way the inductance value can vary proportionally with the ratio of the currents in the coupled lines. A detailed analytical discussion is presented. A...
This paper presents a vertical gate-all-around nanowire FET (VFET) architecture targeting 5nm and beyond technologies, and a new standard-cell construct for digital flow implementation. VFET technology circuits and parasitics for processes and design features aligned with 5nm CMOS are systematically assessed for the first time. Self-aligned quadruple pattering (SAQP) is implemented to achieve required...
Design-Technology co-optimization becomes a key knob to enable CMOS scaling. In this work we evaluate the technology options including lithography options as well as device options that are considered to enable N10 scaling by exploring their impact on representative designs such as standard cells, SRAM and analog contexts. This paper illustrates that the design angle needs to be considered early in...
A 60GHz polar Tx prototype implemented in 40nm CMOS includes a two-stage PA with an RF-DAC, an I-Q upconversion mixer, a 60GHz LO hybrid and a digital synchronization interface. Saturated output power is approx. 10dBm, while RF output and baseband input bandwidths are 9GHz and 1.2GHz, respectively. The linear RF-DAC resolution is 5 bits. EVM degradation and spectral mask out-of-band distortion appear...
This paper reviews some important process aspects of aggressively downscaled FinFET technologies and their implications on digital and analog figures of merits (FOMs). The need to downscale device architectures to enhance digital transistor electrostatics and circuit density led to influences in parasitics, variability, and noise, which impact analog FOMs. Therefore, it is important to understand...
This paper presents an inductorless static 2:1 frequency divider operating up to 60 GHz. In order to save the chip area no peaking inductors are used in this design. Alternatively, to achieve the high operating frequency, the range is extended by asymmetrical sizing of the data and latch transistors and by reducing the load of the following buffer stage. The load reduction is achieved by means of...
A three-stage, transformer-coupled class-AB power amplifier (PA) and a super source-follower-based I-Q upconversion mixer are implemented in 40nm LP-CMOS technology. The transmitter (Tx) front-end is designed for multi-Gbps QPSK/QAM-16 signal transmission at 60GHz with improved back-off efficiency. It achieves 5.7% power-added efficiency (PAE) at 5dB back-off with a total power consumption of only...
This paper presents a flip-flop based static current-mode logic (CML) frequency divider in CMOS using negative capacitance to enhance the performance. We show that thanks to the differential negative capacitance it is possible to compensate partially for the parasitic capacitance at sensitive nodes in the divider. This improves the divider's sensitivity at higher frequencies and increases its self-oscillation...
This paper presents a flip-flop based static current-mode logic (CML) frequency divider in CMOS using negative capacitance to enhance the performance. We show that thanks to the differential negative capacitance it is possible to compensate partially for the parasitic capacitance at sensitive nodes in the divider. This improves the divider's sensitivity at higher frequencies and increases its self-oscillation...
A mm-wave subharmonically injection-locked quadrature oscillator is demonstrated in a 40nm low-power (LP) digital CMOS technology. A large locking range (10GHz), tunable over the 52–66GHz band, is achieved using transformer-coupled resonators. A simple calibration scheme is proposed that only relies on a relative power measurement of the oscillator output signal. The wide locking range, the wide tunability...
The analog baseband section of a receiver for high data-rate 60GHz wireless communications is implemented in 90nm CMOS. It consists of the cascade of a 1st-order transimpedance amplifier with finely programmable gain, a 4th-order source-follower based filter and a coarse gain 1st-order programmable gain amplifier, resulting in an overall 6th-order selectivity and a 1GHz cut-off frequency. Gain can...
An essential part of the bachelor program in Electrical Engineering at the Katholieke Universiteit Leuven since many years is a number of design projects that teach the basics of electronics design engineering to our students. The major project consists of an academic-year-long design task that is carried out by a group of about 20 students. These students are trained to operate as a multidisciplinary...
A phase-locked loop (PLL) that can be used in a zero-IF radio architecture with beamforming for AV-OFDM with 16-QAM modulation is demonstrated for the first time in 40 nm LP CMOS technology. This type II integer-N PLL of order four includes an injection-locked divide-by-4 prescaler and two quadrature series-coupled VCOs, operating in 63-70 GHz and 72-81 GHz frequency bands. It achieves -85 dBc/Hz...
A programmable analog baseband beamformer for a 4-antenna 60 GHz phased-array receiver is implemented in 40 nm digital CMOS. It is based on current amplifiers employing shunt feedback. The phase shifter resolution is better than 20??, with a bandwidth of 1.7 GHz, power consumption of 35 mW, input-referred noise current of 170 nArms and output IP3 of -6 dBV.
A 2.2 GS/S 4??-interleaved 6b ADC in 40 nm digital CMOS is presented. Each ADC slice consists of a 1b folding stage followed by a pipelined binary-search sub-ADC using dynamic nonlinear amplifiers for low power consumption and high speed. Threshold calibration corrects for amplifier and comparator imperfections and 31.6 dB SNDR is achieved with 2 GHz ERBW for 2.6 mW power consumption.
This paper describes the ESAT 2008 Broadcast News transcription system for the N-Best 2008 benchmark, developed in part for testing the recent SPRAAK Speech Recognition Toolkit. ESAT system was developed for the Southern Dutch Broadcast News subtask of N-Best using standard methods of modern speech recognition. A combination of improvements were made in commonly overlooked areas such as text normalization,...
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