Search results for: B.G. Malm

Items from 1 to 14 out of 14 results

chapter

SiC bipolar devices for high power and integrated drivers

M. Ostling, R. Ghandi, B. Buono, L. Lanni, more

2011 IEEE Bipolar/BiCMOS Circuits and Technology Meeting > 227 - 234

2011 IEEE Bipolar/BiCMOS Circuits and Technology Meeting - BCTM

Silicon carbide (SiC) semiconductor devices for high power applications are now commercially available as discrete devices. The first SiC device to reach the market was the unipolar Schottky diode. Active switching devices such as bipolar junction transistors (BJTs), field effect transistors (JFETs and MOSFETs) are now being offered in the voltage range up to 1.2 kV. SiC material quality and epitaxy...

article

Modeling and Characterization of Current Gain Versus Temperature in 4H-SiC Power BJTs

B. Buono, R. Ghandi, M. Domeij, B.G. Malm, more

IEEE Transactions on Electron Devices > 2010 > 57 > 3 > 704 - 711

Accurate physical modeling has been developed to describe the current gain of silicon carbide (SiC) power bipolar junction transistors (BJTs), and the results have been compared with measurements. Interface traps between SiC and SiO₂ have been used to model the surface recombination by changing the trap profile, capture cross section, and concentration. The best agreement with measurement is obtained...

chapter

Comprehensive temperature modeling of strained epitaxial silicon-germanium alloy thermistors

B.G. Malm, M.-R. Kolahdouz, H.H. Radamson, M. Ostling

2009 International Semiconductor Device Research Symposium > 1 - 2

2009 International Semiconductor Device Research Symposium (ISDRS 2009)

Thermistor materials utilizing single-crystalline silicon-germanium alloys, embedded in lowly doped silicon are very suitable for bolometer applications since the inherent noise level is low and exhibits a normal 1/f spectrum. A thermal coefficient of resistance (TCR) value of at least 2%/K can be obtained at room temperature and the performance is directly comparable with nonsemiconductor materials...

chapter

Strain balance approach for optimized signal-to-noise ratio in SiGe quantum well bolometers

L. Di Benedetto, M. Kolahdouz, B.G. Malm, M. Ostling, more

2009 Proceedings of the European Solid State Device Research Conference > 101 - 104

39th European Solid-State Device Research Conference. ESSDERC 2009

This work presents thermal and electrical characterization of SiGe/Si multi-quantum wells (MQWs) with different layer profiles in complete bolometer structures. The thermal property of the bolometers was studied by measuring thermal coefficient of resistivity (TCR) through I-V curves for five temperatures (25, 40, 55, 80 and 100degC) and for four different pixel areas. The results show a strong dependency...

chapter

Towards Schottky-barrier source/drain MOSFETs

M. Ostling, V. Gudmundsson, P.-E. Hellstrom, B.G. Malm, more

2008 9th International Conference on Solid-State and Integrated-Circuit Technology > 146 - 149

2008 9th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT)

This paper provides an overview of metal source/drain (S/D) Schottky-barrier (SB) MOSFET technology. The technology offers several benefits for scaling CMOS, i.e., extremely low source/drain resistance, sharp junctions from S/D to channel and low temperature processing. A successful implementation of the technology needs to overcome new obstacles such as SB height engineering and precise control of...

chapter

Leakage current reduction in 80 nm biaxially strained Si nMOSFETs on in-situ doped SiGe virtual substrates

J. Hallstedt, B.G. Malm, P.-E. Hellstrom, M. Ostling, more

ESSDERC7 - 2007 37th European Solid State Device Research Conference > 319 - 322

ESSDERC 2007. 37th European Solid-State Device Research Conference

We present a comprehensive study of biaxially strained (up to ~3 GPa stress) Si nMOSFETs down to 80 nm gatelength. Well behaved 80 nm devices with expected strain-induced electrical enhancement were demonstrated. Special emphasis was put on investigation of substrate junction leakage and source to drain leakage. In-situ doped wells and channel profiles demonstrated superior substrate junction leakage...

article

Impact of strain and channel orientation on the low-frequency noise performance of Si n- and pMOSFETs

M. von Haartman, B.G. Malm, P.-E. Hellström, M. Östling, more

Solid State Electronics > 2007 > 51 > 5 > 771-777

Mobility and low-frequency (LF) noise were studied in tensile strained Si n- and pMOSFETs fabricated on relaxed SiGe virtual substrates. Both the impact of the channel orientation (〈110〉 or 〈100〉 on (100) Si) and the tensile strain were carefully investigated. Two types of virtual substrates were used; a thin relaxed SiGe layer (20% Ge) and a thick one (27% Ge). The strained Si nMOSFETs fabricated...

article

A robust spacer gate process for deca-nanometer high-frequency MOSFETs

J. Hållstedt, P.-E. Hellström, Z. Zhang, B.G. Malm, more

Microelectronic Engineering > 2006 > 83 > 3 > 434-439

This paper, presents a robust spacer technology for definition of deca-nanometer gate length MOSFETs. Conformal deposition, selective anisotropic dry-etching and selective removal of sacrificial layers enabled patterning of an oxide hard mask with deca-nanometer lines combined with structures defined with I-line lithography on a wafer. The spacer gate technology produces negligible topographies on...

chapter

Device Integration Issues Towards 10 nm MOSFETs

M. Ostling, B.G. Malm, M. von Haartman, J. Hallstedt, more

2006 25th International Conference on Microelectronics > 23 - 28

2006 25th International Conference on Microelectronics

An overview of critical integration issues for future generation MOSFETs towards 10 nm gate length is presented. Novel materials and innovative structures are discussed. Implementation of high kappa gate dielectrics is presented and device performance is demonstrated for TiN metal gate surface channel SiGe MOSFETs with a gate stack based on ALD-formed HfO₂/Al₂O₃. Low frequency noise properties for...

article

Low-frequency noise and Coulomb scattering in Si0.8Ge0.2 surface channel pMOSFETs with ALD Al2O3 gate dielectrics

M. von Haartman, J. Westlinder, D. Wu, B.G. Malm, more

Solid State Electronics > 2005 > 49 > 6 > 907-914

Carrier mobility and low-frequency noise were investigated in Si _0.8 Ge _0.2 surface channel pMOSFETs with ALD Al ₂ O ₃ gate dielectrics. The devices were annealed in H ₂ O vapor, which reduced the negative charge in the gate dielectrics. The carrier mobility was characterized versus change in oxide charge, which allowed an estimation of the Coulomb scattering...

article

Low-frequency noise in Si0.7Ge0.3 surface channel pMOSFETs with ALD HfO2/Al2O3 gate dielectrics

M. von Haartman, D. Wu, B.G. Malm, P.-E. Hellström, more

Solid State Electronics > 2004 > 48 > 12 > 2271-2275

Low-frequency noise was characterized in Si _0.7 Ge _0.3 surface channel pMOSFETs with ALD Al ₂ O ₃ /HfO ₂ /Al ₂ O ₃ stacks as gate dielectrics. The influences of surface treatment prior to ALD processing and thickness of the Al ₂ O ₃ layer at the channel interface were investigated. The noise was of the 1/f type and could be modeled...

article

Characterization of leakage current related to a selectively grown collector in SiGeC heterojunction bipolar transistor structure

E. Suvar, E. Haralson, H.H. Radamson, Y.-B. Wang, more

Applied Surface Science > 2004 > 224 > 1-4 > 336-340

Sources of base-collector and base-emitter leakage current in a SiGeC-based heterojunction bipolar transistor (HBT) with a selectively grown and chemical-mechanical polished (CMP) collector are discussed. Transmission electron microscopy and electrical measurement have been applied to investigate the leakage current. It has been demonstrated that the edge-located defects generated by selective epitaxy...

article

A low-complexity 62-GHz f _T SiGe heterojunction bipolar transistor process using differential epitaxy and in situ phosphorus-doped poly-Si emitter at very low thermal budget

J.V. Grahn, H. Fosshaug, M. Jargelius, P. Jönsson, more

Solid State Electronics > 2000 > 44 > 3 > 549-554

A low-complexity SiGe heterojunction bipolar transistor process based on differential epitaxy and in situ phosphorus doped polysilicon emitter technology is described. Silane-based chemical vapor deposition at reduced pressure was used for low-temperature SiGe epitaxy. Following SiGe epitaxy, the process temperature budget was kept very low with 900 ^o C for 10<space>s as the highest...

chapter

A high speed SiGe HBT process using non-selective epitaxy and in situ phosphorus doped polysilicon emitter: Optimization of device design rules

J.V. Grahn, B.G. Malm, B. Mohadjeri, J. Pejnefors, more

29th European Solid-State Device Research Conference > 1 > 728 - 731

29th European Solid-State Device Research Conference

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