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An ultra-low Ron, sp SOI LDMOS with an improved BV is proposed and its breakdown mechanism is investigated. The device features a variable-k dielectric trench and a P-pillar beside the trench (VK-P). The P-pillar extending from the P-body to the trench bottom not only acts as the vertical junction termination extension (JTE), but also forms an enhanced vertical RESURF (reduced surface field) structure...
Temperature-dependent ON-state breakdown (BVON) loci of AlGaN/GaN high-electron-mobility transistors (HEMTs) were experimentally demonstrated for the first time. With gate-current extraction technique, impact ionization was revealed to be responsible for the ON-state breakdown in our device as the HEMTs is marginally turned on. The characteristic electric-field Ei of impact ionization was extracted...
A Magnesium Doped Layer (MDL) under the 2-DEG channel and a Drain Metal Extension (DME) are proposed to provide a new degree of freedom in the optimization between breakdown voltage (BV) and specific-on-resistance (Ron-sp) in AlGaN/GaN HEMTs. The surface electric field of the proposed structure is distributed more evenly when compare to the MDL-only structure with the same dimensions. A breakdown...
An analytical model for high voltage Thin-film Silicon-On-Insulator (TSOI) lateral devices is proposed in this paper. A new Reduced SURface Field (RESURF) criterion is obtained for TSOI lateral devices with a lateral linear doping in the drift region. The optimum drift doping profile for TSOI lateral devices can be obtained from the new RESURF criterion. The analytical results are in good agreement...
A new Membrane PSOI High Voltage Device with a Buried P+ layer (MBP+ PSOI) is proposed. Breakdown voltage is only decided by lateral breakdown voltage because of the entire removing of silicon substrate under the drift region and breakdown voltage can be improved with increase of the length of the drift region. Introducing of P+ layer can effectively reduce specific on-resistance and silicon window...
This paper reports a novel Super Junction pLDMOS (SJ-pLDMOS) with charge-balanced SJ region at the surface of Variation Lateral Doping (VLD) drift region. SJ region provides a low on-resistance path in the ON-state and keeps charge balance approximately when the doping concentration of p pillars is slightly higher than that of the n pillars during the OFF-state. A significant reduction of the specific...
Multi-recessed gate 4H-SiC MESFETs with a gate periphery of 5-mm are fabricated and characterized. The multi-recessed region under the gate terminal are applied to improve the gate-drain breakdown voltage and to alleviate the trapping induced instabilities by moving the current path away from the surface of the device. The experimental results demonstrate that microwave output power density, power...
A new super junction LDMOS (SJ-LDMOS) on partial silicon-on-insulator (SOI) with composite substrate is presented in this paper. The thin super junction structure on the buried oxide (BOX) provides the surface low on-resistance path, which is attributed to the heavy doping trait of SJ. The N-buffer layer is introduced under the BOX to sustain vertical voltage, which reduces the substrate-assisted...
A novel silicon-on-insulator (SOI) high-voltage device structure and its eliminating back-gate bias effects are presented. The structure is characterized by a compound buried layer (CBL) made of two oxide layers and a polysilicon layer between them. At the high-voltage blocking state, holes collected on the polysilicon bottom interface shield the SOI layer and the upper buried oxide (UBO) layer from...
Taking threshold energy epsivT into accounting for electron multiplying, the formula of silicon critical electric field ES,C is given as a function of silicon film thickness ts from an effective ionization rate alphaeff. ES,C is increasing with the decreasing of ts especially at thinner ts. 2-D simulative and some experimental results as well as the comparing with several other familiar expressions...
An improved 3D tri-gate 4H-SiC MESFETs structure with recessed drift region was proposed. The recessed drift region of the proposed structure is to reduce the channel thickness between gate and drain to increase breakdown voltage as well as to eliminate gate depletion layer extension to source/drain to decrease gate-source capacitance. The DC and RF electrical characteristics of the proposed structure...
Reduced Bulk Field (REBULF) technology is used in the design of lateral power devices to improve breakdown voltage. Since this technology was firstly presented in 2006, this technology has gained widespread attention amongst researchers and has shown to offer good performance in a variety of application domains, especially in bulk silicon and SOI. This paper aims to offer a compendious and timely...
A novel high-voltage thin layer SOI technology based on 1-mum-thick silicon layer and 2-mum-thick buried oxide layer for driving color plasma display panels (PDP) has been developed. High-voltage pLDMOS with thick gate oxide, high- voltage nLDMOS, and low-voltage CMOS are compatible with LOCOS isolation. The proposed technology includes two aspects: first, an implantation after field oxide (IFO) technology...
A new SOI high-voltage power device with a combination of Uniform and Variation in Lateral Doping profiles on Partial Membrane(UVLD PM SOI) is proposed. Its partial substrate under the drift region is etched to release the potential lines below the buried layer, combining uniform and variation in lateral doping profiles, resulting in an enhancement of breakdown voltage while achieving a low specific...
The SOI LDMOSFETs with step doping profiles in drift region have been experimentally investigated. Uniform, single-step and two-step doped drift regions have been designed and fabricated on a same bonded SOI wafer with the top silicon layer of 3 mum and buried oxide layer of 1.5 mum. The experimental devices with two-step doping profile have a breakdown voltage in access of 250 V and specific on-resistance...
A novel concept of REBULF (REduced BULk Field) is proposed for the development of smart power integrated circuit with thin epitaxy layer, and a new device structure of Reduced BULk Field LDMOS with N+-floating layer embedded in the high-resistance substrate is designed. The mechanism of improved breakdown characteristics is that the high electric field around the drain is reduced by N+-floating layer...
A novel SOI high voltage device with compound dielectric buried layer (CDL SOI) and its analytical model is proposed. The vertical electric field of buried layer is enhanced due to the low k (permittivity) of dielectric layer and the electric field in the drift region is modulated by the compound dielectric layer with different k, and both increases breakdown voltage of device. The electric field...
A new high voltage 4H-SiC Schottky barrier diode (SBD) structure for monolithic microwave integrated circuit (MMIC) applications is proposed. It employs one or more floating metal rings (FMRs) which work similar to guard rings. Influence of FMRs structure on the breakdown voltage and cut-off frequencies of the SBD were studied by numerical device modeling. As compared to the one without ring, about...
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