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In this paper, inductive-load switching of a high voltage lateral JFET (HV-LJFET) on 4H-SiC is investigated with a monolithically integrated driver and with an external driver for high frequency, high temperature applications. A new 'capacitor-coupled' gate driver circuitry is proposed and optimized to utilize a standard MOS driver and enable fast switching speed without the need for a negative power...
The chipset presented here offers an integrated 8A/1W gate driver core, direct driving of external n-type DMOS for easy scaling of the gate power and current, as well as control, monitoring and interfacing for a diversity of applications. It also features a semi-custom array containing preconfigured cells and devices to allow application-specific customization. The DMOS are driven by a regulated gate-source...
A new sense device structure is proposed for hybrid IGBTs in which current sensing ratio (CSR) is constant for a wide range of collector currents (ICE)- Hybrid IGBTs are a new type of switching device, with 2 operation modes: MOS operation mode at low ICE and IGBT operation mode at high ICE. Although the current flow mechanism is different between the two modes, it is preferable that CSR in both MOS...
This paper presents an enhanced ESD (electrostatic discharge) protection solution for output drivers without additional protection devices. The output drivers in low and high voltage CMOS technologies are often susceptible against the ESD stresses with and without the ESD protection devices. The proposed structure shows significantly improved ESD immunity using a consolidated NPBL (N plus buried layer)...
A new oscillation circuit has been discovered in switching-mode power supply (SMPS) circuits and is presented for the first time. The new oscillation circuit naturally exists in various SMPS, generates electric oscillation, and, as a result, causes high radiation noise. Small-signal analysis of the new oscillation circuit model was executed and analytical solutions of the oscillation criterion have...
600 V class superjunction (SJ) MOSFETs fabricated by deep-trench etching and epitaxial growth method are experimentally investigated. Planar SJ MOSFETs with both parallel and orthogonal gate structures are fabricated. The SJ MOSFET with parallel gate structure exhibits an improved specific on-resistance of 17 mOmegaldrcm2, which is about 30% lower than that of orthogonal gate structures with the same...
SuperJunction theory predicts that specific on- resistance improves as the widths of the N- and P-type regions in the drift region are reduced. In this paper, it is shown that there is a practical limit to improving on-resistance by shrinking these widths, due to JFET depletion of the conducting regions. An analytic model is developed to calculate the optimum drift region width for super junction...
The solder joint reliability of IGBT chip surface interconnection with a lead-frame structure is described in the power cycling (P/C) capability which is greatly improved due to a chip surface cooling effect in comparison with aluminum wire interconnection. The lead-frame is joined on a Ni and Au plated chip surface with Sn-Ag or Sn-Sb system solders. The P/C capability obtained with the Sn-Sb system...
In this paper, a novel structure based on the Floating RESURF LDMOSFET is proposed for enhanced off-state blocking capability. The new structure facilitates the implementation of FRESURF concept in thicker epi technologies for higher voltage tiers. An additional floating island is introduced, sandwiched between the standard drift region and heavily doped buried layer, which makes the Incremental FRESURF...
In this work, a new design of high voltage (1200 Volts range) power superjunction MOSFET (SJMOSFET) is presented: the deep trench SJMOSFET (DT-SJMOSFET). Besides, a new junction termination, consisting in a 70 mum width and 100 mum depth trench filled by a dielectric, is proposed. Simulation results show that this junction termination exhibits the same blocking voltage capability as the base cell...
We show that the "variation of lateral doping" (VLD) edge termination technique (Fig. 1) exhibits a surprisingly high robustness in the avalanche regime. This is the consequence of a self-limiting time-periodic current filamentation mechanism, which prevents the VLD structure from being destroyed, in contrast to stable stationary current filaments staying permanently at the same location...
An anomalous breakdown voltage degradation has been observed during high temperature gate stress (HTGS) test on 20 V double diffused drain (DDD) P-channel device realized on a 0.18 mum high voltage gate (HVG) platform. The critical role played by the salicide protection and borderless nitride layers has been pointed out by dedicated process trials.
We report on the demonstration of enhancement- mode n-channel lateral implanted GaN high-voltage MOSFET with breakdown voltage up to 2.5 kV or specific on-resistance as low as 30 mOmegaldrcm2. With proper RESURF dose, drain current up to 0.1 A and breakdown voltage up to 1570 V is realized on the same device. The reliability lifetime defined by the failure criteria of DeltaIp/Ip=20% was determined...
We report on the experimental demonstration of a novel n-channel GaN hybrid MOS-HEMT realized on AlGaN/GaN heterostructure on sapphire substrate. This enhancement-mode MOS-gated heterojunction transistor, with 3 mum channel length and 20 mum RESURF length, exhibited a specific on-resistance as low as 20 mOmega-cm2. Simulations indicated the strong dependence of device breakdown voltage on the doping...
This paper reports some simulation results on the cosmic ray induced failure of 3000 V-class silicon diodes using the new direct recombination model which had been used in the simulation of 600 V-class diodes [1], Distinct destruction wave forms were not reproduced. However, an unstable operating mode that was peculiar in a long n- -length diode was found. Regarding this instability as the cause of...
The breakdown voltage of AlGaN/GaN high electron mobility transistors (HEMTs) was increased considerably without sacrificing any other electrical characteristics by proton implantation. The breakdown voltage increased from 416 V of conventional device to 719 V by proton implantation with 150 KeV, 1x1014cm-2 fluence after a thermal annealing at 400degC for 5 min under N2 ambient. The increase of breakdown...
Abstract- 4H-SiC PiN diodes have been manufactured on a Norstel epitaxied P+ZN/N* substrate with a combination of Mesa and JTE as edge termination. A breakdown voltage of 3.3 kV has been measured at lmuA regardless the active area (0.16 and 2.56 mm2). A differential on-resistance of 1.7 mOmega.cm2 was extracted at 15A-25degC. The recovery charge was only of 300 nC for a switched current of 15A at...
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