The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Electrical properties of silicon-dot-based single-electron memory devices were investigated using numerical simulation. For an accurate calculation of tridimensional electron wave functions in the dots and in the dot-isolation surrounding the nextnano++ simulator was employed. Tunneling rates between the dot and other electrodes were calculated using a post-processing of the electron-state-specific...
The electrical performance and reliability of a through-silicon via is investigated through two-dimensional and three-dimensional simulations. Due to the large differences in material thicknesses present in the structures, a 3D simulation is often not feasible. The thermo-mechanical stress, the electrical parameters including TSV resistance and capacitance, as well as the electromigration-induced...
An efficient approach is presented and demonstrated which enables the simultaneous simulation of the impact of several sources of process variations, ranging from equipment-induced to stochastic ones, which are caused by the granularity of matter. Own software is combined with third-party tools to establish a hierarchical simulation sequence from equipment to circuit level. Correlations which occur...
n-channel 4H-SiC MOSFETs were manufactured and characterized electrically at room temperature by current-voltage and Hall-effect measurements as well as by numerical simulations. To describe the observed electrical characteristics of the SiC MOSFETs, Near-Interface Trap (NIT) and charge carrier mobility degradation models were included in the simulation, performed with Sentaurus Device of Synopsys...
In this work we present transient reflectivity measurements, maximum melt depths, and surface topographies of ion implanted silicon samples after pulsed excimer laser thermal annealing in the melting regime. The samples were annealed with different laser energies and number of pulses. We found that the melt dynamics change after the first laser pulse resulting in a shorter melt time but deeper melt...
In this paper we present an extensive comparison of tunneling device simulations versus experimental results. Different tunneling models were used to simulate long channel silicon on insulator tunneling field effect transistors. The results were compared to experimental results, which were taken from the literature. A calibrated parameter set of the dynamic NonLocal-Tunneling model is presented, which...
Ion implantation profiles of boron after a BF3 plasma immersion ion implantation in a plasma implanter with a pulsed voltage ion extraction were investigated both experimentally and by means of numerical simulation. Boron profiles for different ion implantation doses in the range 1015 to 1017 cm−2 were measured using the SIMS method. Simulations were performed using a Monte-Carlo based binary-collision...
The influence of temperature variations during flash annealing on contact resistances in 6-T SRAM cells was studied. TCAD simulations of 32 nm single gate FD SOI devices were carried out. The active regions of a 6-T SRAM cell were simulated by 3D process simulations to calculate the Schottky contact resistances. A coupled spike and flash annealing scheme was used to anneal the devices. Flash annealing...
A simulation study of lithography induced layout variations in 6-T SRAM cells is presented. Lithography simulations of a complete 6-T SRAM cell layout, including active n+/p+ regions layer and poly-gate layer were performed. The smallest feature size was assumed to be 45 nm. 76 positions of the projector focus were simulated for each layer in total. TCAD simulations of 32nm single gate FD SOI MOSFETs...
We demonstrate the coupling of Monte Carlo sputter simulation with feature-scale simulation of profile evolution during sputter etching. With the Monte Carlo sputter simulation, the dependence of the sputter yield on the angle of incidence and on the energy of ions impinging onto the surface is determined. The yield curves obtained thereby are fed into a feature-scale etching profile simulator which...
We demonstrate the coupling of plasma reactor equipment simulation and feature-scale profile simulation for dry etching of silicon in a chlorine plasma. Equipment simulation delivers fluxes of ions and neutrals, as well as the angular characteristics of the ions. These quantities are fed into a feature-scale simulator based on a Monte Carlo approach for determining relevant quantities on the feature...
Source and relevance of process variations are briefly discussed. A combination of own lithography and commercial TCAD simulation software is applied to assess the impact of some of the most relevant variations occurring in lithography on the electrical properties of three kinds of CMOS devices with 32 nm physical gate length.
The simulation of process options for advanced CMOS devices is discussed in this work. Advanced rapid thermal annealing schemes are applied to fully depleted silicon on insulator MOSFETs with a physical gate length of 22 nm. Process induced mechanical stress is simulated for PMOS transistors to improve the Ion-Ioff relation. A modification of the linear piezo model is presented to simulate the hole...
In this study, several morphological parameters to assess the P-wave from the surface electrocardiogram are proposed and analysed. In order to evaluate spatial features, two parameters are defined: P-wave complexity and P-wave residuum. Additionally, in order to evaluate beat to beat features, the P-wave regularity is defined. All three parameters are computed from the eigenvalue decomposition of...
In this paper, a TCAD-based simulation study on lithography process-induced gate length variations has been performed. This study aims at evaluating fully depleted silicon on insulator (FD SOI) MOSFETs for next generation CMOS devices. Critical dimensions (CDs) have been obtained using rigorous lithography simulations. The impact of the resulting gate length variations on the electrical behavior of...
In this work, the influences of advanced annealing schemes, spike and flash annealing and combinations of them, on the electrical behavior of modern FD SOI MOSFETs have been investigated by numerical simulations. Process simulations have been performed for comparing the two-dimensional diffusion behavior of the dopants under the different annealing schemes. Device simulations have been performed for...
A method for decreasing the parasitic source and drain contact resistances in decanano-scaled CMOS devices is presented in this work. The improvement of the electrical performance of the CMOS devices has been achieved by increasing the active contact area, without increasing the complete layout area consumption of the device, for lowering the parasitic source/drain contact resistances. Numerical simulations...
Problems of pre-silicon compact modeling of nano-scaled silicon-on-insulator MOSFETs are addressed using the extraction of SPICE model parameters directly from numerical TCAD simulations. Although there are difficulties in the parameter extraction for the standard SPICE compact models we show by a direct comparison with the results of the numerical mixed-mode TCAD simulations that with some trade-offs...
This paper targets automatic performance tuning of numerical kernels in the presence of multilayered memory hierarchies and single-instruction, multiple-data (SIMD) parallelism. The studied SIMD instruction set extensions include Intel's SSE family, AMD's 3DNow!, Motorola's AltiVec, and IBM's BlueGene/L SIMD instructions. FFTW, ATLAS, and SPIRAL demonstrate that near-optimal performance of numerical...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.