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Recent advances in successful operation of silicon-based devices where transport is dependent on electron magnetic moment, or ldquospinrdquo, could provide a path to a future alternative for logic processing. The basics of this spin-based electronics technology are discussed and the specific methods necessary for application to silicon are described. Mirroring the Haynes-Shockley experiment, which...
In this paper we present, an overview of partial depleted Silicon on Insulator (PD SOI) CMOS transistor technologies for high performance microprocessors. To achieve a ldquohigh performance per wattrdquo figure of merit, transistor technology elements like PD SOI, strained Si, aggressive junction scaling, asymmetric devices need hand-in-hand development with multiple core- and power efficient designs...
Pocket architecture is a useful technique to eliminate short channel effects. However, it has been shown an influence on mismatch performances. In this paper, different implant trials are done on NMOS devices with dose and energy variation. For the first time, the impact of indium implant will be analyzed to optimize mismatch performance. It is demonstrated that this implant decreases significantly...
The impact of fin line-edge roughness on threshold voltage and drive current of LSTP-32 nm Fin-FETs is estimated through TCAD simulations. A Monte Carlo approach highlights an increase in the average VT and a decrease in the average ION w.r.t. sensitivity analysis based predictions. Correlations of fin shape fluctuations to electrical performance are investigated. An equivalent fin width is calculated,...
Previously published 3D simulations of 105 statistical samples have shown distinct asymmetry in Random Discrete Dopant induced threshold voltage variations in Bulk MOSFETs. Based on detailed statistical analysis of the underlying physical processes that shape such distributions we present a robust method, capable of accurately predicting random discrete dopant induced threshold voltage variation out...
In this abstract, the impact of series resistance on mobility extraction in conventional and recessed-gate ultra thin body (UTB) n-MOSFETs is investigated. High series resistance leads to an overestimation of the internal source/drain voltage and influences the measurement of the gate to channel capacitance. A specific MOSFET design that includes additional channel contacts and recessed gate technology...
Accurate effective mobility calculations of MOSFETs are necessary when assessing the importance of various performance limiting carrier scattering mechanisms. A novel and simple to use technique to correct for the absence of drain bias during the split CV measurement is presented. Its effectiveness is demonstrated by application to a quasi planar SOI MOSFET at 300 K and 4 K. The lateral field and...
Thanks to both device simulation and ballistic calculation, the concept of apparent mobility is discussed in the case of unstrained and strained nanoscale DG MOSFET. We show that the apparent mobility reduction in simulated short channel devices can be explained by non stationary effects. The apparent mobility is successfully linked to the long-channel mobility and to a ldquoballistic mobilityrdquo...
A detailed electrical characterization of advanced triple-gate FinFETs focusing on mobility extraction at short gate length and narrow Fin effects is reported. Low temperature measurements in the range of 100 K-300 K and interface quality determination are also performed for better physical insights. In conclusion, the mobility is degraded at small gate length in sub 100 nm FinFETs using parameter...
A methodology for incorporating quantum corrections into self-consistent atomistic Monte Carlo (MC) simulations via the density gradient effective potential is presented. The quantum corrections not only capture charge confinement effects, but accurately represent the electron-impurity interaction used in previous dasiaab initiopsila atomistic MC simulations, showing agreement with bulk mobility simulation...
We analyze the effects of surface roughness on double gate (DG) MOSFETs by means of a full-3D real-space self-consistent Poisson-Schrodinger algorithm within the non equilibrium Green's function (NEGF) formalism. We include periodic (Cauchy) boundary conditions along one of the transverse directions, whereas Dirichlet conditions are imposed along the vertical one. Surface roughness (SR) is included...
The goal of this paper is to present and to analyze the tunnel FET and its specific properties (small subthreshold swing, very low OFF currents). We investigate the opportunities offered by this sub-ldquokT/qrdquo swing device and review the issues that TFET has to overcome (ambipolar behaviour, low ON current) for future circuit applications. For that purpose we report on experimental results on...
Atomistic tight-binding real space and mode space models are used to investigate the key design parameters of graphene nanoribbon tunneling transistors. For an ideal NA = 12 nanoribbon FET, a 1890 muA/mum ON current and an ON/OFF current ratio in excess of 105 can be achieved with VDD = 0.4V. The effect of edge roughness is also investigated showing a deterioration of the device performance, in particular...
Discovery of novel Si nanostructures would open up a new avenue for science and technology as the discoveries of C60 and carbon nanotubes did. With this expectation, we have explored novel Si nanostructures by combining empirical molecular dynamics simulations and structure optimizations with the density functional theory. Our molecular-dynamics simulations demonstrate (1) an icosahedral Si nanodot...
This paper presents fully-depleted short-channel Schottky barrier (SB) MOSFETs with silicidation induced dopant segregation of B at a low temperature of 450degC. The integration of nickel silicide combined with either As or B segregation significantly improves the switching performance of dopant-free SB-MOSFETs. The implantation dose dependence of the device characteristics is studied on long channel...
We study the suppression of ambipolar behavior of Schottky-barrier MOSFETs using an interface engineering approach. Inserting a thin silicon nitride layer between the metallic source/drain electrodes and the silicon yields low Schottky barriers and results in unipolar device characteristics demonstrated with pseudo-MOSFETs. Simulations support the observed suppression and show that with appropriate...
In this paper, the gate-voltage dependent source/drain (S/D) resistance (RSD) in dopant segregated (DS) Schottky barrier (SB) junctions is examined by experiment and simulation. The focus is placed on fully depleted UTB-SOI MOSFETs featuring PtSi S/D with As-DS realized at low temperatures. When modeling SB-S/D with DS, it is challenging to determine if the performance enhancement observed is induced...
With Fermi's golden rule we have calculated the impact ionization (II) rates for strained SiGe. In our approach, the energy and the momentum are exactly conserved during the calculation of the six-dimensional integral in k-space over 4 conduction and 3 valence bands. The wave-vector space is discretized with a very fine grid with a spacing of up to 1/40 (2pi/a), where a is the lattice constant. II...
The use of Ge and III/V materials for future CMOS applications is investigated. Good passivation of the Ge surface can be obtained by either GeO2 or Si passivation. Short channel Ge pMOS devices with low EOT are fabricated using Si passivation at 350 and 500degC. The passivation of III/V materials is a very challenging topic. Some critical issues and passivation schemes are discussed.
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