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MuCCRA-cube is a scalable three dimensional dynamically reconfigurable processor. By stacking multiple dies connected with inductive-coupling links, the number of PE array can be increased so that the required performance is achieved. A prototype chip with 90 nm CMOS process consisting of four dies each of which has a 4 times 4 PE array was implemented. The vertical link achieved 7.2Gb/s/chip, and...
One of the benefits of coarse grained dynamically reconfigurable processor array(DRPA) is its low dynamic power consumption by operating a number of processing elements(PE) in parallel with low clock frequency. However, in the future advanced processes, leakage power will occupy a considerable part of the total power consumption, and it may degrade the advantage of DRPAs. In order to reduce the leakage...
In multi-context dynamically reconfigurable processor array (DRPA), the required number of contexts is often increased by those with low resource usage. In order to execute such contexts without wasting a context memory, we propose a new execution mode called instruction buffer mode in addition to the normal multi-context mode. In this mode, a configuration code from the central configuration memory...
The power consumption of dynamically reconfigurable processing array (DRPA) is quantitatively analyzed by using a real chip layout and applications taking into account the reconfiguration power. Evaluation result shows that processing power for PEs is dominant and reconfiguration power is about 20.7% of the total dynamic power consumption. Based on the above evaluation results, we proposed two dynamic...
A new configuration scheduling algorithm in multicast configuration scheme is proposed and evaluated over reduction ratio of configuration data transfer cycles and power/energy overhead on a coarse-grained dynamically reconfigurable processor array (DRPA). As a case study, the proposed methods are applied to some real applications on a DRPA architecture MuCCRA-1. As a result, we confirmed that the...
In this paper, we propose a dynamically reconfigurable processor Array (DRPA) generator which can generate various types of DRPAs. Our target DRPA architecture is fully parameterized. By specifying architectural parameters, it can automatically generate RTL model, simulation environment, and finally chip layout. In our DRPA generator, although the fundamental design of a processing element (PE) and...
We propose a cryptographic accelerator for IPsec by using the NEC electronics' dynamically reconfigurable processor (DRP). In our system, an embedded processor and DRP are integrated in a system-on-a-chip (SoC) and multiple cryptographic tasks can be accelerated by DRP. Moreover, the virtual hardware mechanism, which dynamically changes its configuration data set, is introduced to realize more tasks...
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