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This paper describes a single-channel, calibration-free Successive-Approximation-Register (SAR) ADC with a resolution of 10 bits at 240 MS/s. A DAC switching technique and an addition-only digital error correction technique based on the non-binary search are proposed to tackle the static and dynamic non-idealities attributed to capacitor mismatch and insufficient DAC settling. The conversion speed...
An increased damping resistor (IDR) replaces high-order loop filter to simply reduce the total harmonic distortion (THD) of Class-D audio amplifier. Besides, cross offset cancellation (COC) technique minimizes the system offset voltage to avoid dc current flows to the speaker in the bridge tied load (BTL) structure. Furthermore, variable switching frequency characteristic in self-oscillating modulation...
A 10Gbps, 1/5-rate burst mode clock and data recovery (BMCDR) circuit is proposed. The BMCDR is reconfigurable between data gating mode and phase tracking mode to achieve instantaneous phase-locking with jitter suppression for 10 GPON. Incorporating a 1/5-rate CDR with 1:5 demultiplexer, it achieves a high energy efficiency of 1.24pJ/bit. With a 4MHz, 0.22UIpp input data jitter, the recovered clock...
This paper presents an ultra low-power transceiver for 20-Gb/s backplane communications. Incorporating half-rate, power-saving transmitter and full-rate, high-speed receiver with 2-stage equalization, this work achieves 21 Gb/s with BER≪10−12 over a 40-cm (16-inch) regular FR4 channel, while consuming a total power of only 87 mW from a 1.2-V supply.
A 2.4 GHz linear CMOS power amplifier (PA) for OFDM WLAN application in 65 nm CMOS technology is presented. The cascode PA operating from 3.3 V employs the proposed asymmetric lightly doped drain MOSFET (A-LDD) structure as common-gate stage to sustain large signal stress and 1.2 V core device as common source stage to provide high frequency operation. Beside, dynamic bias technique is used not only...
A 2.4 GHz fully-integrated MISO transceiver consisting of two receivers and one transmitter is implemented in 0.18 mum CMOS technology. To alleviate the cost of external front-end components, the RF transmit/receive (T/R) switch and a power-efficient linear CMOS PA are fully integrated on-chip. It shows 3.5 dB low noise figures in the receivers respectively. Also, the transmitter delivers an average...
This work presents a single channel (cable) prototype lOGBase-T transceiver fabricated in a 90nm CMOS process. A 1.2V/3.3V dual supply is used. The transmitter, consuming 93.7mW, features a class- AB line driver using an AC coupled bias and a common-mode (CM) compensation capacitor transparent to the differential-mode (DM) path to achieve high efficiency. It achieves 59.51dB SFDR for a test signal...
A 10b 200MS/s folding ADC is implemented with a cascaded folding factor of 4x5 to reduce the number of comparators. A simple offset calibration is developed to avoid the complex calibration loops, improving the settling behavior of the ADC. After calibration, the measured ENL is enhanced from +8M.5LSB to +1.4/-1.5LSB while the SNDR performance is improved from 43.9dB to 54.1dB at input frequency of...
A time-interleaved pipeline ADC is designed with the reconfigurable resolution and sampling rate, Fs, to accommodate different operation scenarios. The main offset and gain mismatches between four sub-ADCs are modulated to the frequency of F/2 by the reference-and opamp-sharing techniques. Fabricated in 90 nm CMOS, the 7 bit ADC has an ENOB of 6.5 at 1.1 GHz sampling rate. The I/Q ADCs totally consume...
A fully integrated transmitter front end with on-chip power amplifier (PA) in 0.18 um CMOS technology is presented. The on-chip PA employs dynamic bias technique to reduce power consumption and enhance linearity. In the measurement, it reveals the output PldB of the PA is 26.5 dBm. Also, the transmitter delivers an average power of 17.3 dBm with EVM of -28.1 while drawing 225 mA of DC current (PA...
An 11 b 800MS/S time-interleaved ADC is implemented in a 90nm CMOS process for a 10GBase-T application. A single open-loop T/H circuit using a cascode source follower achieves high resolution and conversion rate. The offset and gain mismatches are corrected by the digital background calibration. The measured DNL and INL are <0.5LSB and <1.6LSB, respectively. The measured SNDRs are 58 and 54dB...
A low-power full-band 802.11abg transceiver in 0.15mum CMOS technology is presented. It shows 4.4/4dB low noise figures in 2.4/5GHz receiver chains. An on-chip PA (power amplifier) delivers 20dBm output P 1dB -40 to 140degC operation temperature is achieved by sensing technique. On-chip power detector and transmitter to receiver feedback loop estimate I/Q imbalance, and a new I/Q compensation scheme...
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