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This paper overviews the universal mobile telecommunications system long term evolution (LTE) and discusses the requirements for device technologies pertaining to mobile terminals. The LTE represents the next generation cellular phone technology that is intended to achieve a high peak data rate, low latency, and high radio efficiency in addition to low cost and sufficiently high mobility characteristics...
In analog circuits, power consumption is fundamentally related to noise and the signal bandwidth. In this paper, the theoretical minimum and practical power consumption of various implementations of analog circuits is analyzed. Continuous-time and discrete-time implementations of analog circuits are contrasted. Recent circuit approaches such as comparator and zero-crossing-based circuits are also...
A H.264/AVC baseline-profile real-time encoder for HDTV-1080p at 30 fps is implemented with the dedicated hardware engines and one 32-bit Media embedded Processor (MeP) equipped with hardware extensions. The 11.5 Gbps 64 Mb system-in-silicon DRAMA is embedded to alleviate the external memory bandwidth. With TSMC 0.18 m CMOS technology, the SoC core occupies 27.1 mm die area and consumes 1.41 W at...
A multi-core SoC for multi-application (recognition, inference, measurement, control, and security) is developed. The configurable heterogeneous architecture with 9 CPUs and 2 matrix processors reduced 45% power consumption. The performance-oriented multi-bank matrix processor with 2-read-1-write calculation and background I/O operation is adopted. The 1 GHz CPU is realized by the delay management...
This paper presents a LDPC decoder chip supporting all 19 modes in IEEE 802.16e system. An efficient design strategy is proposed to reduce 31.25% decoding latency, and enhance hardware utilization ratio from 50% to 75%. Besides, we propose an early termination scheme that can dynamically adjust the number of iterations. The multi-mode chip can be maximally measured at 83.3 MHz with only 52 mW power...
A heterogeneous multiprocessor on a chip has been designed and implemented. It consists of 2 CPUs and 2 DRPs (Dynamic Reconfigurable Processors). The design of DRP was intended to achieve high-performance in a small area to be integrated on a SoC for embedded systems. Memory architecture of CPUs and DRPs were unified to improve programming and compiling efficiency. 54times AAC-LC stereo encoding has...
Historically buck converters have relied on high-Q inductors on the order of 1 to 100 muH to achieve high efficiency. In this paper we exploit on-chip magnetic coupling in the proposed stacked interleaved topology to enable high efficiency buck converters to be realized with 2 nH moderate-Q on-chip inductors. The measured conversion efficiency for a prototype circuit implemented in a 130-nm CMOS technology...
This paper presents a high efficiency digital controller for a switching type DC-DC converter with excellent static and dynamic performance. This digital PWM controller integrates a PID-like control mechanism and a new predictive interpolation technique to guarantee large signal stability and fast dynamic response. To support the proposed control scheme, an ADC structure that can sequentially sample...
This paper reports a delay locked loop (DLL) based hysteretic controller for high-frequency multiphase buck DC-DC converters. The DLL control loop employs the switching frequency from a hysteretic comparator to automatically synchronize the remaining phases. A dedicated duty cycle control loop is used to enable current sharing and ripple cancellation. We demonstrate a 25-70 MHz 4-phase converter with...
A buck converter with maximum charging current control in achieving high tracking speed is presented. An adaptive delay compensation scheme is employed to keep the switching frequency at 850 kHz within plusmn2.5% across the whole operation range. The integrated buck converter was fabricated using a 0.35 mum CMOS process and all functions are verified by extensive measurements.
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