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This paper presents an ultra low-power transceiver for 20-Gb/s backplane communications. Incorporating half-rate, power-saving transmitter and full-rate, high-speed receiver with 2-stage equalization, this work achieves 21 Gb/s with BER≪10−12 over a 40-cm (16-inch) regular FR4 channel, while consuming a total power of only 87 mW from a 1.2-V supply.
A digital near-end crosstalk (NEXT) canceller merged with an analog equalizer for multi-lane serial-link receivers has been realized in 0.13mum CMOS technology. With the proposed sign-sign block least-mean-square (SSB-LMS) circuit, a 5 Gb/s PRBS of 231mnplus1 suffered from both the channel loss and NEXT for 10-inch FR4 traces is successfully equalized. The measured BER is 10-12 and the measured maximum...
This paper presents the design of a 2.5Gb/s serial link transceiver with a power consumption of 70mW. With IV supply voltage, the transceiver achieves the bit error rate of 10-14. A supply regulated PLL is shared by the transmitter and the receiver to facilitate the low-power and low-voltage design. The output jitter of the transmitter is 53.9ps peak-to-peak and the chip area is approximately 0.54...
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