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An extremely low energy/operation, single cycle 32 bit/word, 128 Kbit SRAM is fabricated in 90 nm CMOS. In the 850 MHz boost mode, energy consumption is 8.4 pJ/access. This reduces to 3.6 pJ/access in the normal 480 MHz mode and bottoms out at a very aggressive 2.7 pJ/access in the 240 MHz low power mode. This performance is obtained using novel, digitally tunable sense amplifiers and a tunable timing...
This paper presents a 60 GHz digitally controlled phase shifter in the 65 nm CMOS technology. Using a differential varactor-loaded transmission-line architecture, the phase shifter achieves a phase resolution of 22.5deg, an average insertion loss of 8.5 to 10.3 dB and a return loss of better than 10 dB from 55 to 65 GHz. The phase shifter occupies an area of only 0.2 mm2. To the knowledge of the authors,...
A 10 bit 165 MS/s pipelined ADC without a dedicated sample and hold is presented. Op-amp sharing and a single ended reference buffer loaded with a resistive divider are used. The ADC consumes 56 mW and occupies 0.15 mm2. It is fabricated in a 90 nm 1.2 V CMOS process and achieves 55 dB SNR for a 60 MHz input. A novel measurement technique called ldquopad noise suppressionrdquo is introduced to prevent...
This paper presents the first standard CMOS flash analog-to-digital converter (ADC) operational over an ultra wide temperature range (UWT) from room temperature (27deg C or 300 K) down to 4 K (-269deg C). To preserve the circuits performance over the UWT range in the presence of temperature induced transistor anomalies, dedicated architecture and switching schemes are employed.
The first time-domain successive approximation register (SAR) smart temperature sensor is proposed in this paper. Without using any bipolar transistor, a temperature sensor composed of temperature-dependent delay line is utilized to generate a delay time proportional to the measured temperature. A binary-weighted time reference delay line is adopted for set-point programming. The effective delay of...
We present an on-chip word line (WL) dual supply system for server class embedded DRAM (eDRAM) applications. The design consists of switched capacitor charge pumps, voltage regulators, reference and clock circuits. Charge pump engines feature efficient charge transfer and energy conversion, boosting unregulated rails to 1.8x supply. At vdd=1 V, regulated high (1.5 to 1.7 V) and low (-0.3 to -0.6 V)...
Class D audio amplifiers provide high quality audio signals with very good efficiency. This makes them not only useful for high power home audio equipment and television, but also for battery powered portable devices. This paper shows details of an analog signal processor for a class D output stage which provides the audio output for a hands-free amplifier in mobile telephones. Two differential stages...
In this paper, a solution to realize a low-power programmable frequency divider using dynamic logic is proposed. By cascading compact dual-modulus divider slice with recursive feedback mechanisms, any dividing ratio is easily implemented. A 5-stages 0.18 mum CMOS implementation demonstrates a power consumption factor as low as 235 nW/MHz under 1.2 V supply for high dividing ratios.
The design of a 100 kHz frequency reference based on the electron mobility in a MOS transistor is presented. The proposed low-voltage low-power circuit requires no off-chip components, making it suitable for Wireless Sensor Networks (WSN) applications. After one-point calibration the spread of its output frequency is less than 1.1% (3sigma) over the temperature range from -22degC to 85degC. Fabricated...
This paper presents a low-power CMOS RF front-end for 3-5 GHz non-coherent impulse-radio ultra-wideband (IR-UWB) receiver. The proposed front-end comprises a variable-gain low noise amplifier (VG-LNA), an active balun and an analog squarer. Current reuse topology has been adopted in both VG-LNA and active balun to reduce the power consumption. The squarer design is based on the quadratic law of MOSFET...
This paper presents a low power, high speed and high resolution SiGe DDS MMIC with 11-bit phase and 10-bit amplitude resolutions. Using more than twenty thousand transistors, including an 11-bit pipeline accumulator, a 6-bit coarse DAC and seven 3-bit fine DACs, the core area of the DDS is 3 times 2.5 mm2. The maximum clock frequency was measured at 8.6 GHz with 4.2958 GHz output. The DDS consumes...
In this paper, a technique is proposed to suppress the fractional spur induced by non-linearity of the loop in all digital PLLs (ADPLLs). The measurement results show that the fractional spurs are reduced by at least 9 dB, to below -75 dBc, when the technique is applied to a conventional all digital PLL (ADPLL) at 3.6 GHz. The extra silicon area needed for technique is only 0.02 mm2.
A DC/DC boost converter to power integrated circuits is presented. It can boost extremely low voltages, starting from about 150 mV. The converter is based on a new hybrid inductive and capacitive architecture and it is suitable for power harvesting applications. A test chip was designed and fabricated using a UMC 180 nm low threshold CMOS process. Measurements on the chip confirm the validity of the...
This paper presents an integrated ultra-low power analog frontend architecture for UWB impulse radio receivers. The receiver is targeted towards applications like wireless sensor networks and body-area networks typically requiring ultra energy-efficient, low data-rate communication over a relative short range. The proposed receiver implements pulse correlation in the analog domain to severely relax...
A low-power FM-UWB receiver front-end for low data rate (100 kbps) short-range (<10 m) applications operating in the upper UWB band at 7.45 GHz is described. The front-end comprises a 21 dB gain preamplifier and a 1GHz bandwidth FM demodulator. The measured receiver sensitivity is -86.8 dBm while consuming 9 mW from a 1.8 V supply and -84.3 dBm is achieved at 6 mW power consumption. The 0.88 mm...
A digital delay-locked-loop (DLL) suitable for generation of multiphase clocks in applications such as time-interleaved and pipelined ADCs locks in a very wide (40X) frequency range. The DLL provides 12 uniformly delayed phases that are free of false harmonic locking. The digital control loop has two stages: a fast-locking coarse acquisition is achieved in four cycles using binary search; a fine linear...
A novel imaging technique is proposed for fully digital detection of phase and intensity of light. A fully integrated camera implementing the new technique was fabricated in a 0.35 mum CMOS technology. When coupled to a modulated light source, the camera can be used to accurately and rapidly reconstruct a 3D scene by evaluating the time-of-flight of the light reflected by a target. In passive mode,...
We present a fully integrated Phase Locked Loop in an advanced 45 nm CMOS technology. The loop filter is integrated on chip under the voltage-controlled oscillator inductor, resulting in significant area savings. The whole PLL measures only 280 mum by 150 mum. The PLL has a dual-band output for 2-2.5 GHz and 4-5 GHz. The circuit operates from a 0.85 V supply and consumes 15.3 mW for a -120 dBc/Hz...
This paper presents a new hybrid current-programmed, current-output active pixel sensor (APS) suitable for real time X-ray imaging (fluoroscopy) and an off-panel CMOS readout circuit. The pixel circuit is designed using hydrogenated amorphous silicon (a-Si:H) thin film transistor (TFT) technology. Measurements show that the proposed pixel circuit can successfully compensate for characteristic variations...
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