Serwis Infona wykorzystuje pliki cookies (ciasteczka). Są to wartości tekstowe, zapamiętywane przez przeglądarkę na urządzeniu użytkownika. Nasz serwis ma dostęp do tych wartości oraz wykorzystuje je do zapamiętania danych dotyczących użytkownika, takich jak np. ustawienia (typu widok ekranu, wybór języka interfejsu), zapamiętanie zalogowania. Korzystanie z serwisu Infona oznacza zgodę na zapis informacji i ich wykorzystanie dla celów korzytania z serwisu. Więcej informacji można znaleźć w Polityce prywatności oraz Regulaminie serwisu. Zamknięcie tego okienka potwierdza zapoznanie się z informacją o plikach cookies, akceptację polityki prywatności i regulaminu oraz sposobu wykorzystywania plików cookies w serwisie. Możesz zmienić ustawienia obsługi cookies w swojej przeglądarce.
3D integration opens up new opportunities for future multiprocessor chips by enabling fast and highly scalable 3D Network-on-Chip (NoC) topologies. However, in an aim to reduce the cost of Through-silicon via (TSV), partially vertically connected NoCs, in which only a few vertical TSV links are available, have been gaining relevance. In addition, the number of vertical paths can be expected to be...
With NoCs (Networks-on-Chips) becoming a central part of today's many-core systems, ensuring a good level of performance at the routing level has never been so crucial. In previous works, we have introduced a novel method for designing fully adaptive deadlock-free routing algorithms for NoCs called ESPADA (EScape PAths with Dynamic channel Acquisition). The strength of our approach lies in its ability...
As the number of processing elements in modern chips keeps increasing, the evaluation of new designs will need to account for various challenges at the NoC level. To cope with the impractically long run times when simulating large NoCs, we introduce a novel GPU-based parallel simulation method that can speed up simulations by over 250×, while offering RTL-like accuracy. These promising results make...
NoCs (Networks-on-chips) are considered as the paradigm of choice for on-chip communication as they solve the scalability concerns of traditional buses. Many research efforts have been aimed toward the design of adaptive routing algorithms that are flexible enough to avoid congested and defective areas in a NoC. However, to avoid deadlocks, most of these solutions either prohibit some turns, which...
NoCs (Networks-on-Chips) are being viewed as the paradigm of choice for on-chip communication in modern SoCs (Systems-on-chips). Unfortunately, continuous technology downscaling is rendering NoC components increasingly susceptible to failure, to a point where it is no longer an option to design such systems without accounting for reliability issues. In this work, we concern ourselves with faults affecting...
NoCs (Networks-on-Chip) are an attractive alternative to communication buses for SoCs (Systems-on-Chip) as they offer both high scalability and low power consumption. However, designing such systems in the nanoscale era brings up some serious concerns about reliability. Our aim is to design robust NoCs while limiting performance degradation. In this paper, we introduce several techniques meant to...
Podaj zakres dat dla filtrowania wyświetlonych wyników. Możesz podać datę początkową, końcową lub obie daty. Daty możesz wpisać ręcznie lub wybrać za pomocą kalendarza.