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The Internet of Things (IoT) is an extremely fragmented market and can be defined as anything from sensors to small servers. It is estimated that over 30 billion IoT devices will ship by 2020. The ability to sense countless amounts of information that communicates to the cloud is driving innovation into IoT applications, such as in wearable devices (for health, fitness or infotainment applications)...
Given today's fast growing automotive semiconductor industry, this tutorial will discuss the implications of automotive test, reliability and functional safety requirements on all aspects of the SOC lifecycle: design, silicon bring-up, volume production, and particularly in-system functional safety. Today's automotive safety critical chips need multiple insystem self-test modes, such as power-on self-test...
We are delighted to present the 2016 11th International Design and Test Symposium (IDT) which is organized this year in Hammamet city, Tunisia, December, 18–20, 2016.
The semiconductor industry has been driving a major part of its growth through first the PC and more recently the mobile market. Unfortunately, the PC market is in decline and also the end of the growth curve for mobile products is in sight now that virtually everyone on the planet has a smartphone and/or tablet. Hence, the semiconductor industry is putting its bets on ‘Internet of Things’ (IoT) as...
Today's IoT design teams, use heterogeneous IP blocks from numerous sources in several-levels of hierarchy. To ensure manufacturing quality and filed reliability for such IoTs, DFT designers adopt new test solutions across heterogeneous IP, which is meant to enable concurrent test, power reductions during test, DFT closure, isolated debug and diagnosis, pattern porting, calibration, and uniform access...
In this paper, we proposed an approach to reduce the hardware required by the conventional algorithm CRESTA (Comprehensive Real-time Exhaustive Search Test and Analysis) by trying to share the hardware between different sub-analyzers. Experiments with synthesis for the case of three spare rows and three spare columns evidenced for saving at least 15% of hardware, and for the case of two spare rows...
Dr. Yervant Zorian is a Chief Architect and Fellow at Synopsys. Formerly, he was a Distinguished Member of Technical Staff AT&T Bell Laboratories, Vice President and Chief Scientist of Virage Logic, and Chief Technologist at LogicVision. He is currently the President of IEEE Test Technology Technical Council (TTTC), the founder and chair of the IEEE 1500 Standardization Working Group, the Editor-in-Chief...
Fault tolerant (or dependable) computing has always been an exciting research area in the intersection of computer science and engineering and electrical and electronics engineering. During the last two decades the applicability of the methods and tools that the fault tolerance research community produces has expanded to virtually all application domains. The type of fault tolerance methods employed...
Presents the introductory welcome message from the conference proceedings. May include the conference officers' congratulations to all involved with the conference event and publication of the proceedings record.
Due to their spatial structures, FinFETs have several advantages including controlled Fin body thickness, low threshold voltage variation, reduced variability and lower operating voltage. Because of the special structures of FinFET transistors, modern FinFET-based memories can lead to defects that require new test and repair solutions. Usually the existing approaches are not able to provide appropriate...
In the year 2013, IEEE Test Technology Technical Council (TTTC) took an initiative to establish a forum involving young professionals (both from industry and academia) working in the broad domain of manufacturing test, diagnosis, debug, yield improvement and related areas. We organized panel meetings in conjunction with VLSI Test Symposium (VTS) and International Test Conference (ITC) last year to...
With technologies shrinking and design complexity increasing, it becomes crucial that embedded in chip test and repair solutions keep up with the advances in order to consistently provide superior chip quality and yield optimization. The embedded test approaches developed for designs done a few years ago are not sufficient for today's designs, which are bigger, faster, hierarchical and much more sensitive...
IEEE Test Technology Technical Council (TTTC) takes an initiative to establish a forum involving young professionals working in the broad domain of test, diagnosis, yield improvement and related areas. We have formed a panel involving a diversified group of young professionals (recent PhD graduates from US and Canadian universities) currently employed in the leading US semiconductor and EDA companies...
As process technologies continue to shrink and design complexity grows, today's designs present a unique set of test challenges including higher test costs, higher power consumption during test, lower design productivity and new defects at small geometries. The designs are larger and using multiple processor cores in SoCs to enable the next generation of mobile internet devices. Each core contains...
This session brings together specialists from the DfT, DfY and DfR domains that will address key problems together with their solutions for the 14nm node and beyond, dealing with extremely complex chips affected by high defect levels, unpredictable and heterogeneous timing behavior, circuit degradation over time, including extreme situations related with the ultimate CMOS nodes, where all processor...
In this talk, an overview of the latest advances in SAT technology will be provided. Specifically, the input format of SAT solvers and the common SAT algorithms used to solve decision/optimization problems will be described. In addition, the speaker will highlight the use of SAT algorithms in solving a variety of EDA decision and optimization problems. This should guide researchers in solving their...
How can the semiconductor industry improve the communication between what is done up front in the design, and what is done downstream in the fab and during test? This panel will examine whether product test can provide the necessary "grand unification" to solve today's broken handoffs between DFM, test chips, and fab yield management systems. Questions addressed include: What does the "grand...
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