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Aspergillosis of the skull base is an unusual disease entity, mainly found in immunocompromised patients. Aspergillosis originating in the pterygopalatine fossa (PPF) without contiguous spread from the sinuses is extremely rare. A 79-year-old woman complained of having suffered pain in her left cheek and headaches for 4 months. Computed tomography (CT) scans revealed soft tissue filling the left PPF...
We measured instant VΛ change coming from the relaxation effect in high-k dielectric layer in CTF. A counter-pulse scheme was proposed to solve the issue in CTF memory, by inserting short positive gate pulse between erase execution pulse and verify read step, whose validity was confirmed in our NAND test vehicle main cell array.
In this paper, the data retention characteristics of the charge trap flash (CTF) memory are evaluated and new findings to predict its lifetime more accurately are reported. In addition, the unique charge loss behavior of CTF memory cell is explained in terms of charge loss paths.
The local electron trapping in the select transistors used in the Charge Trap Flash (CTF) NAND was analyzed in depth for the first time in terms of operation conditions and gate spacer process. In this work, we examined the mechanism of swing degradation in the select transistors with TANOS (TaN-Al2O3-Si3N4-SiO2-Si) structure due to repetitive program/erase [P/E] operation. The swing degradation can...
The symmetric inversion-type S/D structure has been employed for achieving available program disturbance for scaled NAND flash memory beyond sub-40 nm node. The inversion S/D structure enables the channel doping to be reduced due to non-existence of n-lateral diffusion and it suppresses charge sharing between program-inhibit channels, resulting in superior program disturbance. Moreover, the cells...
Charge trap flash (CTF) memory is one of the most promising technologies for the next generation NAND technology. Among various CTF memories, excellent manufacturability of TaN-Al2O3-Si3N4-SiO2-Si (TANOS) structure has been successfully developed by achieving 32Gb MLC NAND flash using 40nm technology node (Y. Park et al., 2006). 3 dimensional NAND cells such as hemispherical corner (HC) (D. Kwak et...
In the proposed new scheme, which is named self aligned trap-shallow trench isolation (SAT-STI), such process damage on high-k layer can be minimized, achieving the goal of isolating the storage nitride layer successfully.
It was found that the charge loss behavior of TANOS (TaN-Al2O3-nitride-oxide-silicon) cells for NAND flash memory application is highly dependent on the gate structures for the first time. The gate structures with trap layers remained on source and drain regions showed increased charge loss compared to the one with trap layers separated between different gate lines. The improvement by removing the...
A highly manufacturable 32Gb multi-level NAND flash memory with 0.0098 μm2 cell size using 40nm TANOS cell technologies has been successfully developed for the first time. The main key technologies of 40nm 32Gb NAND flash are advanced high N.A immersion photolithography with off-axis illumination system, advanced blocking oxide of the TANOS cell, and PVD tungsten and flowable oxide for bit line
For the first time, multi-level NAND flash memories with a 63 nm design rule are developed successfully using charge trapping memory cells of Si/SiO2/SiN/Al2O3/TaN (TANOS). We successfully integrated TANOS cells into multi-gigabit multi-level NAND flash memory without changing the memory window and circuit design of the conventional floating-gate type NAND flash memories by improving erase speed....
A new 64-cell NAND flash memory with asymmetric S/D (Source/Drain) structure for sub-40nm node technology and beyond has been successfully developed. To suppress short channel effect in NAND memory cell, asymmetric S/D consisting of optimized junction and inversion layer induced by fringe field of WL bias which is applied at NAND operation conditions is successfully utilized. 64-cell NAND string which...
To realize TANOS-NAND flash memory, key requirements like program/erase speed, read retention, and program disturb window should be satisfied. In this work, we present 63 nm NAND-type TANOS cells to satisfy all the requirements and to replace floating-gate cells in conventional NAND flash memory without changing a circuit design and a sensing window
A NAND-type MONOS device has been successfully developed by breakthrough technologies including optimized cell structures and integration schemes providing favorable memory cell structures and peripheral circuits. In this study, optimized TANOS (TaN-Al2O 3-nitride-oxide- silicon) cells integrated using 63nm NAND flash technology showed high performance compatible to floating-gate (FG) cell. The newly-developed...
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