The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Presented is the vision to qualitatively and quantitatively define the nonvolatile memory and storage markets strategy. The aim is to bridge or translate the concepts of the nonvolatile memory and storage technologies from research and development into component manufacturing, to implementing these components into memory sub-systems and quantifying the market applications usage and its impact on the...
The NAND flash memory occupied 40% of the total flash memory market with an annual growth rate of 70% in 2004, while NOR flash achieved only more modest growth rate of 30%. It is expected that NAND flash will surpass the market share of NOR flash in the flash market for the first time in 2005. From the viewpoint of market trend, NAND flash will be more popular in future because of more diversified...
A new simple and low cost logic based single poly flash memory technology (NeoFlashreg) with fast programming and high reliability is demonstrated in this paper. With merely 3 additional noncritical masks, the SONOS based technology has been successfully embedded into 0.18mum CMOS logic process. Hot electron injection is utilized to achieve fast programming. Uniform channel tunneling erasure and hot-hole-free...
NAND flash memory based solid-state disk (NSSD) has been used for industrial and military use due to its high reliability and shock resistance. With the bit cost reduction of flash memory and the explosive growth of flash market, NSSD is expected to penetrate into diverse applications such as mobile thin clients, car navigation systems and movie players, which prefer low power consumption, high reliability,...
In this work, we present a novel buried BL (BBL) concept that links the source contacts of each individual BL via the isolated p-well; thus effectively eliminating one metal line per BL and reducing overall cell size. In comparison to the UCPE cell, a conservative cell size shrink of about 40% can be achieved from a standard embedded 21F2 DT-UCPE-cell. The schematic cell layout is shown and comparison...
A novel embedded one-time programmable (OTP) nonvolatile memory (NVM), using only standard Foundry CMOS logic technology, is described. IP modules with densities from 1Kb to 1Mb were constructed and tested. Reliability data is presented for 1Mb memory modules fabricated in 0.18mu technology
The existing embedded nonvolatile memory technologies have failed to deliver a cost effective solution for SoC applications. The major reason has been that most of these technologies were not designed specifically for the embedded applications. There have been two approaches for the embedded nonvolatile memories. One is to take the high density stand alone memory technology and use it for embedded...
A new programming disturbance phenomenon in the NAND flash cell operation is introduced, which we have modeled and named as "source/drain hot-carrier injection disturbance" (abbr. "hot-carrier disturbance"). The source/drain hot electrons are supplied from gate-induced drain leakage current at the GSL (ground-select line) transistor gate edge and are accelerated in the source/drain...
A new high cost-performance NAND Flash memory using 3-level MLC and virtual page cell architecture has been proposed. It provides 20% die size saving and 3 times fast program speed compared to conventional SLC and MLC, respectively. The proposed method can be a good choice of the market demanding both low cost and high performance as well as high reliability
Recently the cell integration density of NAND flash memory increases rapidly due to its simple structure suitable for high resolution lithography. However as the cell integration density increases, NAND flash memory cell shows the problem of increased parasitic capacitance between the cells. The problems are generated by the floating-gate interference during cell operation. In order to reduce the...
One of the most important performances of NAND flash memory is reliability characteristics, such as program/erase cycling and data retention. Tunnel oxide quality is essential to the reliability and it is well known that tunnel oxide degradation during FN (Fowler-Nordheim) stress is due to the oxide trap and interface trap generation. It is believed that trapping mainly occurs where tunnel oxide is...
A recent report reveals that in source-bias erase flash cells, light source doping can cause room temperature erratic charge loss after program/erase cycling. In this paper, we present tunnel oxide hole trapping and stress induced leakage current (SILC) measurements under source-bias erase stress conditions, in cell structures with different source doping profiles. Data suggests the deep depletion...
In this paper, we discuss the reliability evaluation and qualification results of a small (~ 256b) pFET based floating gate nonvolatile memory for embedded application in a UHF RFID chip that is being volume produced using a foundry logic CMOS process. The memory is based on bi-directional Fowler-Nordheim tunneling using a ~65-70 Aring oxide that is available from typical foundry processes with 3...
Reliability and performance of both NAND and NOR flash memories strongly depend on the physics of Fowler Nordheim (FN) tunneling, a mechanism widely used in writing operations. In fact, the large number of involved cells and the strong sensitivity to technological parameter variations cause wide threshold voltage distributions after FN tunneling. Overerase, erratic phenomena and tunnel oxide degradation...
Flash memories are difficult to embed in advanced CMOS generations, which is largely due to the nonscaling high program and erase (P/E) voltages; typically VPEap15V for cells operated by Fowler-Nordheim (FN) tunneling. Besides, for memories of only a few Mbytes, the need for these high voltages leads to a bad array-to-periphery area efficiency, resulting in a relatively large module size. Therefore,...
A novel SONOS device with nitrided hafnium silicate (HfSiON) as top and bottom dielectric, used in memory arrays up to 26kbit, is reported for the first time. Compared with `classical' SONOS, where the nitride-trapping layer is sandwiched between silicon oxide (SiO2 ) (Libsch, 1998), these memory arrays show excellent performance, especially for data retention
In this work, we demonstrate for the first time the operation of memory cells with a bidirectional engineered tunneling barrier: a triple layer Variot stack. Furthermore, these memory cells also have an Al2O3 interpoly dielectric and achieve 10 years of data retention up to 120degC
To realize TANOS-NAND flash memory, key requirements like program/erase speed, read retention, and program disturb window should be satisfied. In this work, we present 63 nm NAND-type TANOS cells to satisfy all the requirements and to replace floating-gate cells in conventional NAND flash memory without changing a circuit design and a sensing window
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.