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We propose a novel architecture (phase change nonvolatile SRAM: PNSRAM) combining SRAM with PRAM. This architecture is possible solution to reduce the program cycle at the nonvolatile material to be divided a program sequence into volatile and nonvolatile. In this paper, we describe the PNSRAM architecture and a circuit simulation results of the volatile and nonvolatile operation
In addition to the huge resistivity changes, the phase-change switching process is accompanied by a significant volume change (Pedersen et al., 2001), which in turn can result in large stresses. This can become a serious reliability issue, particularly in small device cells utilizing under- and over-layers of suitable contact metals. It is important then to evaluate the magnitude and the sign of stress...
Nitride based, localized charge trapping storage flash memory devices with a SONOS stack get increasingly interest due to some advantages compared to conventional floating gate memory devices (Eitan et al., 2000). One of these is the ability to store multi bits in one single cell. There are several previous attempts to simulate and to measure the lateral extend of the localized charges. For the first...
The hysteretic resistance switching characteristics of Pt/Nb-doped STO Schottky junctions were investigated for nonvolatile memory applications. The Pt/single crystal Nb:STO Schottky junction exhibits excellent resistance switching characteristics such as stable pulse switching, uniform set/rest state and die-to-die uniformity. The switching mechanism might be explained by modulation of the Schottky...
In terms of nonvolatile memory device characteristics, the optimal device parameters for the TWISTOR (twin SONOS transistor) structure are investigated. Through this study, we show the best performance of 80nm gate TWISTOR device, which are very promising solution of future 2-bit/cell SONOS technology
A novel embedded one-time programmable (OTP) nonvolatile memory (NVM), using only standard Foundry CMOS logic technology, is described. IP modules with densities from 1Kb to 1Mb were constructed and tested. Reliability data is presented for 1Mb memory modules fabricated in 0.18mu technology
NAND flash memory based solid-state disk (NSSD) has been used for industrial and military use due to its high reliability and shock resistance. With the bit cost reduction of flash memory and the explosive growth of flash market, NSSD is expected to penetrate into diverse applications such as mobile thin clients, car navigation systems and movie players, which prefer low power consumption, high reliability,...
In this work, we present a novel buried BL (BBL) concept that links the source contacts of each individual BL via the isolated p-well; thus effectively eliminating one metal line per BL and reducing overall cell size. In comparison to the UCPE cell, a conservative cell size shrink of about 40% can be achieved from a standard embedded 21F2 DT-UCPE-cell. The schematic cell layout is shown and comparison...
Reliability and performance of both NAND and NOR flash memories strongly depend on the physics of Fowler Nordheim (FN) tunneling, a mechanism widely used in writing operations. In fact, the large number of involved cells and the strong sensitivity to technological parameter variations cause wide threshold voltage distributions after FN tunneling. Overerase, erratic phenomena and tunnel oxide degradation...
In this paper, two NAND-type PHINES flash memory architectures (1 bit/cell and physically 2 bit/cell) are proposed for mass storage applications. PHINES nitride trapping storage flash memory features high storage density, low power operation, good reliability, simple process, and high programming throughput. Fifteen-nm generation is feasible for future flash memory technology
In this paper, we present a generalized scaling analysis for phase change memory in analytical forms which are verified by 3D finite-element electrothermal modeling. Our analytical solutions provide insights into the key device parameters that control the maximum temperature of the phase change memory cell and the minimum required programming voltage
A two bit/cell embedded nanocrystal bitcell with low write current SSI program and tunnel erase in which nanocrystals are located under dedicated control gates has been demonstrated. Write bias conditions which mitigate gate disturb in a top erase capable bitcell have been confirmed
To realize TANOS-NAND flash memory, key requirements like program/erase speed, read retention, and program disturb window should be satisfied. In this work, we present 63 nm NAND-type TANOS cells to satisfy all the requirements and to replace floating-gate cells in conventional NAND flash memory without changing a circuit design and a sensing window
We have proposed a new method to prepare thin nitrogen-based charge trap layer for scaled-down SONOS with thin EOT (<12nm). Devices employing an ONO prepared by the newly proposed method, a N2-plasma treated base oxide topped by an HTO, showed unprecedented Vth uniformity, carrier localization and good retention characteristics. An overall comparison with Si3N 4-SONOS is given. They also offer...
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