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Modern SOCs may be composed of hundreds of individual physical modules, referred to as tiles. The total number of scan channels servicing these tiles often greatly exceeds the number of SOC device pins available to connect those channels to test equipment. Traditional reliance on a small number of pin-to-channel test mode configurations, predetermined in hardware, results in inefficient scan data...
Through four use cases with examples, we describe how IEEE 1687 can be extended to include analog and mixed-signal chips, including linkage to circuit simulators on one end of the ecosystem and ATE on the other. The role of instrumentation, whether on the tester or on the device itself, is central to analog testing, and conveniently also the focal point of IEEE 1687. We identify enhancements to the...
This article proposes a small digital circuit that can be added to each ADC/DAC parallel port to provide fast streaming serial access and facilitate efficient ATPG. The circuit connectivity can be described in IEEE 1687's instrument connectivity language.
Modern SOCs may be composed of hundreds of individual physical modules, referred to as tiles. The total number of scan channels servicing these tiles often greatly exceeds the number of SOC device pins available to connect those channels to test equipment. Traditional reliance on a small number of pin-to-channel test mode configurations, predetermined in hardware, results in inefficient scan data...
An analog test bus and serial digital access to ADC and DAC parallel ports are two widely used analog DFT techniques. Unfortunately, they cannot be described in a standard way that could facilitate automatic test pattern generation (ATPG). Furthermore, serially accessing an ADC/DAC is typically too inefficient for periodic sampling for various reasons, but mostly because of the capture/update-then-shift...
This paper provides an overview of a flow to generate and apply cache-resident self-test (CReST) patterns on a CPU as an alternative to deterministic functional patterns. This paper also compares CReST patterns against deterministic functional patterns, including the results of a case study of applying both CReST and deterministic functional patterns on commercially available AMD x86 processors in...
The high-technology industry in general, and its infrastructure aspects (such as testing) in particular, have recently garnered skepticism with respect to the ability to continue to innovate. This talk will analyze the sources of such criticism, along with possible antidotes, especially the role of “magical thinking” (as popularized in the recent biography of Steve Jobs). The distinction between fantasy...
As chips are getting increasingly complex, there is no surprise to find more and more built-in DFX. This built-in DFT is obviously beneficial for chip/silicon DFX engineers; however, board/system level DFX engineers often have limited access to the build in DFX features. There is currently an increasing demand from board/system level DFX engineers to reuse chip/silicon DFX at board/system level. This...
The use of low-cost structural Fmax measurement as a replacement for in-system Fmax measurement for speed binning has been aided by the use of a data-learning approach that can be used to build a reliable system Fmax predictor given structural Fmax. This paper uses industry test measurements to demonstrate why a data-learning approach for correlation is better than simple correlation approaches, how...
Power-only defects do not cause logical failures in a chip but induce more power consumption. For battery-driven semiconductor chips and others with military-level quality requirements, power-only defects have to be screened out during manufacturing test. To reduce the associated test cost, structural test of those defects is a must. With a dedicated example, this paper demonstrates two methods to...
The effort to standardize a methodology for accessing embedded instrumentation as IEEE PI687 continues to progress. This paper captures the current state of mind of the IJTAG working group with respect to the framework built to date and presents a discussion of other issues on which decisions are pending. The key elements of an architectural description language, a procedural language, and a hardware...
The performance of high-speed serial data links, along with the architectures of the transmitter and receiver circuitry used on either end, has led to increasing difficulty in applying traditional test and measurement techniques to characterize these channels. One solution, explored in this work, utilizes stimulus generation and response analysis circuitry embedded in the devices driving and receiving...
The past two decades have seen a steady stream of challenges and responses in the test field. This paper surveys selected key problems and the progression of their solutions, in both topical and intrinsic aspects, with the aim of performing a meta-analysis of the nature of test innovation. The significant track record of success demonstrated by the industry will be put under serious pressure as technology...
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