The performance of high-speed serial data links, along with the architectures of the transmitter and receiver circuitry used on either end, has led to increasing difficulty in applying traditional test and measurement techniques to characterize these channels. One solution, explored in this work, utilizes stimulus generation and response analysis circuitry embedded in the devices driving and receiving the links to perform a variety of tests and measurements that match and even exceed those possible with traditional instruments, as actual silicon results demonstrate. The access to this embedded measurement circuitry is provided via the IEEE std. 1149.1 test access port by use of a possible prototype for the draft IEEE P1687 (IJTAG) standard. This access mechanism is explained and its wider applications for test and debug are explored