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An improved Source Follower based low-pass Sallen-Key continuous time biquadratic cell is presented. An innovative structure with auxiliary path is proposed in order to increase the out-of-band attenuation of Sallen-Key filter. The auxiliary path eliminates one out-of-band parasitic zero in the transfer function. A prototype of Sallen-Key second order filter with a bandwidth of 120MHz and a quality...
In this paper a 4th-order low-pass continuous-time analog filter is presented. A smart and compact biquadratic cell has been realized using the super-source-follower circuit. The biquadratic cell synthesizes a 2nd-order low-pass transfer function, using only two capacitors and four transistors per stage: two transistors for gm-C transfer function and two transistors as current sources for biasing...
Analog filters are widely used in several kinds of integrated mixed-signal systems, since they are intrinsically needed for in-band signal selection, out-of-band noise rejection and anti-aliasing for the A-to-D (D-to-A) conversion.
<?Pub Dtl?>The upgrade of the Pierre Auger Observatory required a larger number of detectors that implies a dramatic increase of the power consumption. As the analog-to-digital converter (ADC) is the most critical circuit block, an integrated solution is here proposed. A 10 b 50-MSps 5-stage pipeline ADC is implemented in 65 nm digital CMOS. It achieves 50.3 dB signal-to-noise and distortion...
In this paper a dedicated integrated front-end for the Triple-GEM (Gas Electron Multiplier) detector is presented. The design has been realized in 0.13 μm CMOS technology. This system aims to improve performance with respect to the state-of-the-art on these types of detectors, regarding adaptability, portability, power consumption and on-chip data processing. The front-end is composed by 8-input-channels...
This paper presents a low power transmitter for Impulse-Radio Ultra-Wideband (IR-UWB) applications. It generate short duration bi-phase modulated UWB pulses with a center frequency of 4.5 / 8 GHz according to the selected channel. A simplified transmitter architecture enabling low power consumption has been adopted. The key circuit is a phase shifter used to obtain positive and negative pulses. Generated...
In this paper a 4th order low-pass continuous time analog filter in CMOS 28nm technology is presented. The filter complies with the specifications of the 60GHz next-generation transceivers. A novel circuital topology is presented suitable to perform the low-pass filtering of the in-band signal, while the in-band thermal noise is high-pass filtered, improving Signal-To-Noise-Ratio. 880MHz −3dB bandwidth...
This paper describes a chopper stabilized amplifier, obtained using an input chopper for modulation, an AC coupling for offset rejection and a correlated double sampling structure for demodulation, avoiding ripple spurs. The operational amplifier has a rail-to-rail input stage, with a supply voltage range from 1.8V to 5V. It is characterized by a multipath nested Miller compensation network with double...
A 10b 100-MS/s five-stage pipeline analog-to-digital converter (ADC) is implemented in 65nm digital CMOS process with power-reduction techniques for high energy physics experiments. It achieves 6.9dB signal-to-noise and distorsion ratio (SNDR). 8.5dB signal-to-noise ratio (SNR), 9.2 effective number of bits (ENOB) for a full-scale input sine at nyquist frequency. The ADC power consumption is 12.7mW...
A calibration free, high resolution second-order multichannel Incremental A-to-D-Converter with multi-level quantizer is presented. The system is designed for biomedical application and combines the advantages of low oversampling ratio with SC design solution, like multi bit topology and accurate opamp design. An optimal decimation filter to minimize the weighted sum of thermal and quantization noise...
A calibration circuit for single-ramp A-to-D converters is presented here. The calibration circuit allows to automatically compensate the process/mismatch and radiation effects on the A-to-D converter, improving performance and Equivalent Number of Bits. In particular, the calibration circuit is able to automatically align the ramp signal reference used for the conversion in single slope architectures...
In this paper a 5th order low-pass continuous time analog filter in CMOS 45nm technology is presented. The filter design is based on a single compact cell used to synthesize five poles. The circuit performs the low-pass filtering of the in-band signal, while the in-band thermal noise is high-pass filtered, improving Signal-To-Noise-Ratio. 1-GHz −3dB-bandwidth is obtained by a prototype of the filter...
The design of an automatic biasing system for High-Electron-Mobility-Transistors is here presented (HEMT-Biasing-System, HBS). The HBS automatically regulates the operating point of an off-chip multistage HEMT block. A proper automatic algorithm is implemented in order to maximize the HEMT transconductance (gm) efficiency (defined as gm/IDS ratio). This is an important feature in several HEMT-based...
The A-to-D converter here presented is part of a bigger system able to sense and monitor electrical/physical parameters in particles detectors, for LHC experiments.
In this paper a complete Matlab-Based-Model of a high resolution second-order multi- channel incremental A-to-D-Converter is presented. The A-to-D-Converter model includes the most relevant non-idealities for future transistor- level implementation. The reference technology used for the model is the 90nm CMOS node. The analog part of the A-to-D-Converter will be implemented by switched-capacitors...
A high performance analog front-end for intelligent tyre MEMS accelerometer sensor is presented in this paper. The analog front-end is part of a bigger System-On-Chip totally integrated inside the car tyre, with the aim to interchange real time data with the car central unit. Such system is intrinsically self-biased (a vibration-based scavenger device is used), so that a very low power budget is available...
In this paper a Charge-Sensitive Preamplifier (CSP) for GEM (Gas Electron Multiplier) detectors readout is presented. The CSP is responsible for signal acquisition and the conversion of the input charge into a voltage signal. The design has been realized in 0.13 µm CMOS technology. It has been demonstrated through a detailed analysis that this is the best CMOS technology to be used in this case, as...
A low power front-end for GEM (Gas Electron Multiplier) detectors has been developed in 0.13µm CMOS node. The front-end sensitivity is 0.5mV/fC which remains almost unchanged up to a 15 pF detector parasitic capacitance. The input dynamic charge range varies from 30fC to 1pC including only a single (negative) polarity charge. The front-end provides as output signal two different time-domain square-wave...
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