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The low reliability of advanced CMOS devices has become a critical issue that can potentially supersede the benefits of the technology shrinking process. This is making the design time reliability assessment and optimization a mandatory step in the IC design flow. As part of our ongoing research, we describe an algorithm based on probability analysis and logic principles for computing the impact of...
This paper presents a novel Computer-Aided-Design (CAD) framework for 3D extraction of the substrate electrical network. The proposed CAD tool (framework) models efficiently the minority carrier propagation inside substrate network especially for smart power ICs. Today, the minority carrier propagation into the substrate is ignored in existing SPICE simulators. It can be simulated using finite element...
Audio Amplifier in portable systems (i.e. Mobile Phones) or in thermally close environment (i.e. car radio) faced the historical problem of low efficiency while using linear amplifier classical approach such as Class A/B/AB. In latest year the adoption of Class-D switching amplifier has been widely accepted for their higher efficiency (∼90%) thus removing the problem of wasting power and thermal dissipation...
In this paper a fully differential current conveyor based switched capacitor (SC) integrator is presented. To operate the current conveyor (CCII) integrator with high linearity, calibration is used to correct for its non idealities. Simulation results are presented to show the effectiveness of the calibration technique. The presented integrator is applied to design of a 2nd order Delta Sigma ADC....
This paper describes the implementation of a calibratable charge-redistribution (CR) based successive-approximation-register (SAR) analog-to-digital converter (ADC). This differential 13-bit CR SAR ADC is implemented with a unit capacitance of 1.54 fF which is much smaller than the capacitance used in most novel SAR ADCs. As a result, the area and the power consumption are reduced significantly. In...
A new architecture for differential bandgap voltage references is presented. The system is based on a switched capacitor amplifier that performs correlated double sampling to cancel offset and reduce flicker noise while maintaining a valid output voltage throughout the clock cycle. The circuit noise is filtered by an intrinsic discrete time low-pass function with tunable cut-off frequency. A prototype...
A current-mode delta-sigma modulator is presented for electrochemical sensor arrays utilizing a Current Conveyor and a Current Controlled Oscillator (CCO). Second order noise shaping is achieved although a very simple topology is used with only one integrator. The impact of oscillator non-linearity is kept low thanks to a pseudo-differential design. Simulations predict an SNDR of 102 dB at 10 kHz...
In this work, all MOS current reference circuit is proposed using a standard 0.18 µm technology and the simulations were performed using the Cadence Spectre simulator. The proposed current reference circuit is based on, the resistorless current reference circuit suggested by Oguey and Aebishcher. The Oguey's circuit is capable of generating the reference current in a nanoampere range, but with the...
A novel design combining embedded high dielectric constant dielectric resonator with planar technologies is presented in this paper. The utilization of dual-mode embedded resonators with high dielectric constant allows interesting miniaturization possibilities while maintaining a competitive filter performance. The proposed design is compatible with LTCC and, in general, any planar technology such...
We present a design study for the fabrication of a fully depleted CMOS image sensor integrated on high-resistivity epitaxial layer. Both models and simulations are used and show that the maximal depleted thickness and the punch-trough current are dependent on the photo-diode cathode length. From these considerations, achievable performances are estimated.
In the race to deliver ever smaller and faster devices, bulk FinFETs are seen as a viable alternative to planar bulk technologies. With that in mind, a new benchmarking scheme is implemented in order to effectively and fairly compare, in simulation, a 10nm FinFET technology with a 28nm planar CMOS one on a 100 MHz gain-bandwidth operational amplifier. For identical phase margins, the 10nm design consumes...
This work focuses on the analysis of a periodically switched cross-coupled nMOS oscillator when periodic initial conditions are applied. Based on a classical Van der Pol model of the oscillator, an analytical solution is used that takes into account the time dependency of the instantaneous amplitude and frequency. This leads to a model for pulsed oscillations generated by the initial conditioned and...
Power converters based on Wide Bandgap Devices (WBD) are able to operate at high-frequency and high-voltage. In such synchronous converters a very short dead-time is advised because a lot of WBD do no have a parasitic body diode to conduct current in reverse. Into a high-voltage inverter, isolators generate isolated floating gate signals from logic level input signals. Mismatch between high-side and...
We present an innovative sensor chip, exploiting backside illumination of a silicon-on-insulator (SOI) wafer integrating custom single photon avalanche diodes (SPADs), flipped and wafer-bonded on a standard CMOS wafer integrating the analog front-end circuit, in-pixel digital processing and readout electronics. Two major improvements are achieved: higher pixel density and fill-factor, since these...
CMOS Single Photon Avalanche Diodes (SPADs) are a dedicated type of photodetectors that are attracting increasing interest. Crosstalk and fill factor are magnitudes that become important when dealing with arrays of SPADs. There are trade-offs that involve these two magnitudes and dark count rate (DCR) which are of great interest for the implementation of image sensors. A set of 5×5 matrices of SPADs...
Actually, in the mobile application area, the reduction of power consumption appears to be a bottleneck when designing transceiver architectures for those systems. This is especially true when considering two large parts of the actual electronics market: Wireless Sensors Networks (WSN) and Internet of Things (IoT). Both of them require wireless communications and a large autonomy while being battery-powered.
A novel and simple circuit topology is presented for high-speed, floating, high voltage level shifters. It uses a current mirror plus latch circuit composed of two inverters. Simulations based on AMS 0.18 µm High Voltage (HV) CMOS Technology show this circuit to combine high speed, low power dissipation, and small layout area. The simulation results show the propagation delay to be below 150 ps for...
Probabilistic behavior of logic gates represents one of the main reliability problems associated to CMOS circuits supplied at very low supply voltages. This paper aims to analyze the impact of probabilistic faults in interconnects, by means of HDL saboteur-based simulated fault injection (SFI). We propose four types of saboteurs: the simplistic probabilistic type, a switching type - aware and two...
We propose a method for the formal reset sequence verification for digital asynchronous circuits. First the traditional approach for the reset verification is discussed and the need for a novel solution is shown. The proposed method is based on the extension of the standard logic types with a multi-value logic type and a source code instrumentation method. The method is finally applied to an exemplary...
It's our pleasure to welcome you to the 10th conference on Ph. D. Research in Microelectronics and Electronics (PRIME 2014). This event, dedicated to Ph. D. Students in Microelectronics takes place in Grenoble, France, from June 30th to July 3rd. Grenoble is the capital of the French Alps and fifth World's Most Inventive City (Forbes).
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