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In this paper, a study of the leakage current through strained p+ n Si1-xGex/Si hetero-junctions is presented. The reduction in the band gap, induced by stress forces, and the doping level at the hetero-interface, due to the use of halo implantations, are varied by changing the Ge content and the recess depth. A comparison between simulation results and experimental data is presented to analyze the...
Channel Hot Carrier (CHC) and Negative Bias Temperature Instability (NBTI) degradation has been studied in pMOSFETs with and without channel strain. The results show larger CHC degradation and a neglegible influence of NBTI on strained pMOS devices. The degradation effects are modeled to be introduced in a circuit simulator. The simulations of a CMOS inverter, which has been chosen as example circuit,...
The low-frequency (LF) noise behaviour of pMOSFETs fabricated in strained Ge (sGe) and reference thick Ge-on-Si epitaxial layers has been compared. As is shown, the LF noise in the subthreshold regime is higher for the reference devices compared with the sGe, while in strong inversion, similar noise levels are achieved. The better noise performance in weak inversion is related to the lower density...
The use of Ge and III/V materials for future CMOS applications is investigated. Good passivation of the Ge surface can be obtained by either GeO2 or Si passivation. Short channel Ge pMOS devices with low EOT are fabricated using Si passivation at 350 and 500degC. The passivation of III/V materials is a very challenging topic. Some critical issues and passivation schemes are discussed.
This work studies the analog performance of uniaxially and biaxially strained single-gate fully depleted SOI nMOSFETs and standard and strained Si (sSOI) n-type triple-gate FinFETs with high-?? dielectrics and TiN gate material. The analysis is performed focusing on some important analog figures of merit such as transconductance, Early voltage, output conductance and intrinsic voltage gain. It is...
The ESD sensitivity of 65-nm fully depleted SOI MOSFETs (with thin silicon body) used as output buffer devices is studied. A detailed electrical investigation is carried out in order to classify the observed failure modes and mechanisms. We propose a new failure criterion that allows us to univocally identify the device failure. Finally, we analyze the impact of device geometry and strain engineering...
We analysed heavily doped p+/n junctions in germanium, and found that the halos in this work provide a tradeoff between transistor channel control and junction leakage. Temperature-dependent leakage measurements show that either trap-assisted tunneling (TAT) or band-to-band-tunneling (BTBT) are the dominant leakage mechanisms for junctions with halos, (junction doping above ~ 1018 cm-3). Further,...
The downscaling of CMOS below 45 nm has triggered the use of high-mobility substrates in order to compensate the mobility degradation related to the implementation of high-k dielectrics. Strain engineering has become a very popular technique to boost up the mobility and drive current. This paper discusses the electrical performance of junctions and transistors processed in strained Si on thin (250-350...
Here, a systematic study is made of the leakage current in huge-area SiGe-Si p+-n junctions. As will be shown, both the perimeter and area leakage current density are a sensitive function of the S/D etch depth, whereby a higher leakage is obtained for deeper trenches. This can be explained by the presence of dislocations at the SiGe-Si interface, as revealed by transmission electron microscopy (TEM)...
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