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Uniaxial stressors have been mainly employed for boosting PMOS performance, while it is more difficult to increase NMOS performance using tensile stressors. This results in changing the n:p ratio, which requires circuit layout changes. Enhancing both NMOS and PMOS performance to retain the same n:p ratio is desirable. Interactions between biaxial lattice strain, uniaxial relaxation, process-induced...
The interest in the Ge/Si heterostructures with self-assembled islands is associated with their potential use for Si-based optoelectronic devices. Due to the effective hole 3D confinement a photoluminescence (PL) signal from Ge(Si) islands was observed up to room temperature. However, only holes are effectively localized in Ge(Si) islands, while electrons are only weakly confined in Si on the heterojunction...
In the last decade, fabrication technology of microelectromechanical system (MEMS) was greatly developed and various devices have been demonstrated. Epitaxial MEMS structure is one of the variations of MEMS structure. The epitaxial MEMS has some advantages such as atomically flat surfaces and possibility of direct implementation of circuitry on the MEMS structure. In this work, we fabricated an epitaxial...
Silicon germanium on insulator (SGOI) is a straightforward material for ultimate device scaling. This substrate combines two advantages: high carrier's velocity of the Si1 - xGex alloy and low parasitic capacitance due to the presence of a buried oxide. Several fabrication techniques for SGOI substrates, as SMOX, SMART-CUTtrade or liquid phase epitaxy have been proposed. Tezuka et al. present a new...
SiGe on insulator (SGOI) is a typical template substrate for strained Si-on-insulator (SOI) structures, which can enjoy both benefits of the mobility enhancement by strained channels and the low junction capacitance by SOI structures. In order to fabricate the high performance MOSFET, formation of the highly strained Si layers on SGOI without dislocations and defects is quite important. This means...
Quantum dots in silicon/silicon-germanium offer several potential advantages for quantum computing, including long spin coherence times and compatibility with silicon device fabrication. Recently, it has become possible to use Schottky gates to define quantum dots in Si/SiGe heterostructures at low temperatures. Here we describe progress in the fabrication and measurement of silicon quantum dots,...
The addition of high speed laser pulsing and a local electrode geometry has transformed the 3D atom probe into a characterization tool that is capable of analyzing Si-based nanostructures on an atom-by-atom basis (K. Thompson, 2005 and K. Thompson, 2006) . Doped and undoped SiGe structures were successfully analyzed in three dimensions with the laser assisted local electrode atom probe (L2EAP). The...
Globally strained (tensile) silicon-on-insulator (sSOI) is being studied extensively to obtain higher performance CMOS. sSOI offers three key advantages over bulk-Si: (i) reduced parasitic capacitance; and (ii) enhanced electron mobility; and (iii) compatibility with ultra thin SOI device design. Conventionally, sSOI is fabricated by wafer bonding and layer transfer of strain Si. Although this technique...
Among the new architectures that are under development for the very advanced technological nodes, the SON transistors are very promising, insofar as they allow a better electrostatic control of the conduction, compared with standard MOSFETs. The consequence is a limited power loss, which is desirable for mobile devices applications. Several publications from Monfray et al. describe the SON concept...
Semiconductor wafer direct bonding combined with mechanical grinding of the donor wafer and chemical etching of the remaining silicon as well as the SiGe layer is an alternative to the hydrogen-induced layer transfer (HILT). This process allows a larger window for thermal treatments. In combination with modified insulator layers also improvements of the electrical properties and optimized strain engineering...
In the present paper studies of Seebeck coefficient in heavily doped Si1 - xGex (x=0.01-0.05) solid solution whiskers in temperature range 4.2-500K were fulfilled to design temperature sensors operating in wide temperature range
Our experiments demonstrate that Schottky-barrier reducing mechanisms can be overcome by adequately designed Si/SiGe heterostructures and that single electron transistor (SET) functionality can be achieved in modulation-doped Si/SiGe heterostructures with a standard split-gate approach that can easily be integrated into an array of coupled SETs
Further insight into strained layer relaxation processes have been achieved in this work. Effects of surface roughness, dislocation velocities, and dislocation nucleation have been de-coupled. In order to achieve low threading dislocation density with a high degree of relaxation, we are forced to create structures that introduce a high degree of lattice mismatch at the surface, i.e. a gradient in...
In summary, the ~1.5 mum Ge QD MOS LED which is fully compatible with ULSI process is reported for the first time. The origin of the emission is due to the radiative recombination between the electrons and holes confined in the Ge QD. The electrons also recombined with holes at the Si/oxide interface and the band edge light emission from Si is also observed
Two important technologies are exploited in the high-speed SiGe BiCMOS fabrications based on the inspection of the device physics. The effective reduction of the base resistance is achieved by optimizing profile and configuration of the SiGe HBT. Moreover, the concept of obtaining a narrow base in the BiCMOS process is established, which enables the ultra-high-speed SiGe BiCMOS
A new analytical expression for current gain including the neutral base recombination is developed for SiGe HBTs. With the constant Ge content constraint, the optimal Ge profile for the maximum current gain is found to be dependent on both base doping concentration and the total Ge content
Ge-MISFETs have attracted much attention as next generation MOSFETs because of their higher carrier mobility than Si-MOSFETs. However, it has been regarded as extremely difficult to form a gate stack structure with good quality because surfaces of Ge and the oxide films are very unstable thermally and chemically. Therefore, establishment of a surface passivation technique is one of the most important...
In this work, we report the demonstration of a novel CMOS process with substrate-strained-SiGe pMOSFET and mechanical-strained Si nMOSFET fabricated on one chip. The device structure combines the advantages of compressively SiGe materials and tensile Si induced by SiN layer to achieve higher carrier mobility. Moreover, due to the separation process of two kind devices, individual MOSFETs was tuned...
In this paper, we report a simple and CMOS compatible method for forming Ge QDs using selective oxidation of SiGe and demonstrated significant memory effects in the related Ge nc metal-oxide-semiconductor capacitors (MOS-Cs). It is known that Si is preferentially oxidized during high-temperature oxidation of SiGe alloy and the Ge segregation, induce Ge atom pile-up along the SiGe/SiO2 interface....
In this paper, we report the width dependence of short channel effect in strained-Si nMOSFETs. The trade-off between electron mobility enhancement and SCE control for various Ge contents and Si-cap layer thicknesses in the relaxed SiGe buffer are demonstrated. Finally, our work presents the optimum processes window for strained-Si device in advanced CMOS technology
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