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Immersion solder bumping, a mask-less and low cost processing, brings feasibility to the ultra-fine pitch chip-to- chip interconnection; however, how to make the uniform micro-bump is still a great challenge. In this paper, the uniform micro-bumps with very thin Sn-3.0Ag-0.5Cu (SAC305) solder layer on electroless nickel under bump metallization (UBM) are achieved. The test chips we used have 6,507...
In this paper, a construction of 3D array memory module based on chip-on-film (COF) bonding and carrier stacking is developed. Experimental results are demonstrated on an 1.8" HDD-identical platform, where the total thickness of the stacked 3D array memory module of 8 chips X 8 layers is less than 2 mm at 1.8"-HDD area. All materials to implement this 3D array memory for SSD are lead-free...
To prevent potential yield loss, achieve TSV with higher aspect ratio, improve the bonding reliability, and reduce the process cost, a clamped through silicon via (C-TSV) interconnection for stacked chip bonding is proposed and developed in this paper. The metal cap on pad design can not only be a bonding layer for other stacked die on it, but also performs as a protection stopper for blind vias drilled...
Wafer level chip stacked module by embedded IC packaging technology was studied in this paper. Wafers were treated to less than 50 mum thickness and then singulated. The prepared thin chips were stacked on to the base wafer and then embedded by dielectric layers (Ajinomoto build up film, ABF) lamination. Vias to both the pads on the analog chips and digital wafers were done by UV laser drilling process...
This study was aimed to realize the influences of microstructure and shear speed on the fracture behavior of solder ball. The shear behavior of Sn-37Pb, Sn-0.3Ag-0.7Cu, Sn-1Ag-0.5Cu, Sn-3Ag-0.5Cu and Sn-3Ag-0.5Cu-0.06Ni-0.01Ge in solder joint on ball grid array substrate was investigated with differently high shear speed from 10 mm/sec to 1000 mm/sec. The shear speed was found to have strong effect...
By properly incorporating wafer level package (WLP) and chip embedded processes, a type II chip-in-substrate package (CiSP) without ultra-thin chips is developed for high speed memory devices in this paper. According to the design concept of the type II CiSP, a hybrid process using build-up technologies in wafer level and COG-based (chip-on-glass) transfer bonding is explored to implement the JEDEC-compliant...
In this paper, chip to wafer stacking and embedding active components by wafer level technologies were described. The radio frequency (RF) module-like component was chosen as the test vehicle in this study. Analog wafer were treated to less than 50 mum thickness and then singulated. The thin chip were die bonded, by chip stacking method, on to the digital wafer and embedded by lamination of dielectric...
Optical interconnects (OI) prove ways to overcome the high power consumption, large footprint, high integration density, signal latency and skew issues at high speed data transmission. In this paper, the research accomplishments of optical polymer waveguide, high speed optoelectronic packages, rigid and flexible optoelectronic printed circuit board (OEPCB) for high speed board to board, and chip to...
A flexible active E/O local bus module using multi-mode optical transmission performs an interconnection of flexible electronic-optical circuit board in board-to-board level. The proposed E/O module is compatible with traditional electrical interface in printed circuit board(PCB) and can be directly used in high speed module interconnection. A 17 cm long prototyping of the proposed E/O local bus module...
In this paper, a flexible active E/O local bus module using multi-mode optical transmission is proposed to perform board-to-board, chip-to-chip, or board-to-chip optical interconnection with compatibility to traditionally electrical interfaces. In this proposed scheme, high speed modules or chips on tradition printed circuit board (PCB) can be directly interconnected through a flexible active E/O...
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