The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
This paper presents an integer linear programming approach to transistor placement problem for CMOS standard cells with objectives of minimizing cell width, wiring density, wiring length, diffusion contour roughness, and misalignments of common ploy gates. Our approach considers transistor pairing and transistor placement simultaneously. It can achieve a smaller number of transistor chains than the...
The demand for high-density electronic applications is growing. This work develops a novel chip-on-flex (COF) package with sidewall-insulated Au-coated polyimide (PI) compliant-bumps. A double-layer anisotropic conductive adhesive (ACA) material that meets the assembly requirement is adopted for the ultra-fine pitch interconnects. A process for manufacturing 20- μm pitch compliant-bumps is proposed...
Recently, the three-dimensional chip stacking technology with fine pitch and high input/output interconnects has emerged due to the requirements of multi-function and high performance in electronic devices. When the electronic packaging technology develops toward the miniaturization trend, the reliability of interconnect with fine pitch and high density solder bump interconnections will become a critical...
The board-level reliability of a 6-layer polyimide-based coreless flip chip package assembled on a printed circuit board (PCB) under a temperature cycling condition of -55 ~ 125??C was investigated in this study. The assembly of coreless flip chip package was achieved by a 17 mm ?? 17 mm die with 4355 Sn37Pb solder bumps, an amine-based underfill and 1521 Sn3.0Ag0.5Cu solder balls, no defect such...
A novel process which combined wafer level package technology with ultra-fine pitch chip-on-flex (COF) by sidewall-insulated compliant bumps was developed. We laminated two types of adhesives, single-layer non-conductive adhesive (NCA) and double-layer of non-conductive adhesive/anisotropic conductive adhesive (NCA/ACA), on wafers, respectively. After wafers with laminated adhesives were diced into...
A flip chip package was assembled by using 6-layer laminated polyimide coreless substrate, eutectic Sn37Pb solder bump, two kinds of underfill materials and Sn 3.0 Ag 0.5 Cu solder balls. Regarding to the yield, the peripheral solder joints were often found not to connect with the substrate due to the warpage at high temperature, modification of reflow profile was benefit to improve...
This study was aimed to realize the influences of microstructure and shear speed on the fracture behavior of solder ball. The shear behavior of Sn-37Pb, Sn-0.3Ag-0.7Cu, Sn-1Ag-0.5Cu, Sn-3Ag-0.5Cu and Sn-3Ag-0.5Cu-0.06Ni-0.01Ge in solder joint on ball grid array substrate was investigated with differently high shear speed from 10 mm/sec to 1000 mm/sec. The shear speed was found to have strong effect...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.