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This work reveals the impact of quantum mechanical effects on the device performancce of n-type silicon nanowire transistors (NWT). Here we present results for two Si NWTs with circular and elliptical cross-section. Additionally we designed both devices to have identical cross-section in order to provide fair comparison. Also we extended our discussions by reporting devices with five different gate...
New method to extract the amount of floating (FG) charge (QFG) apart from oxide trapped charge (Qox) generated by program and erase (P/E) cycles is proposed, for the first time. QFG shift by P/E cycling shows asymmetry between programmed and erased states as follows; QFG exhibits the peak at ~100 cycles in programmed state, while QFG monotonically reduces in erased state. Next, the midgap voltage...
UTBB FDSOI technology is a faster, cooler and simpler technology addressing the performance/energy consumption trade-off. In this paper we present the main front-end-of-the-line knobs to scale down this promising technology to the 10nm node.
A nonvolatile memory based on ink-jet printed In-Ga-Zn oxide (IGZO) thin film transistor with bottom gate bottom contact architecture is reported. The memory device contains SiO2 gate dielectric layer embedded with silicon nanocrystals, which act as charge trapping sites. Memory effects were observed by a clockwise loop in Vgs-Id curves, which is attributed to the charging and discharging of the silicon...
Unlike MOSFETs, tunnel-FETs (TFETs) are not limited by a 60 mV/dec subthreshold swing and therefore scaling the supply voltage beyond the MOSFET's 1 V plateau becomes feasible. Supply voltage scaling is a necessary condition for reducing the power consumption per transistor, which enables further size scaling of the FETs. Designing a successful FET is however challenging, because it is not sufficient...
In this paper, a 200 nm n-channel inversion-type self-aligned In0.53Ga0.47As MOSFET with a Al2O3 gate oxide deposited by Atomic Layer Deposition (ALD) is demonstrated. Two ion implantation processes using silicon nitride side-wall are performed for the fabrication of the n-type source and drain regions. The 200 nm gate-length MOSFET with a gate oxide thickness of 8 nm features the transconductance...
A leading edge 45 nm CMOS system-on-chip (SOC) technology using Hafnium-based high-k/metal gate transistors has been optimized for low power products. PMOS/NMOS logic transistor drive currents of 0.86/1.08 mA/um, respectively, have been achieved at 1.1 V and off-state leakage of 1 nA/um. Record RF performance for a mainstream 45 nm bulk CMOS technology has been achieved with measured fT/fMAX values...
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