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FPGA emulation has proven to be a performance effective method to analyse the behaviour of digital circuits in the presence of soft errors due to SEU effects. In particular, the recently developed autonomous emulation techniques allow the classification of thousands and even millions of faults per second. In this paper, an approach to extend the autonomous emulation techniques to circuits with embedded...
A possible method to design a Borden code checker is to map the Borden code words to words of an AN arithmetic code and to check the obtained words with an appropriate AN code checker. For t equiv 2 we show how this method can be modified such that a Borden code checker achieves the self-testing property under very weak conditions. It is only required that no checker input line gets a constant signal...
Main stream scan test technology development has focused on a cost-efficient usage of external testers in conjunction with minimized on-chip pattern generators. Alternatively, an on-chip test processor that works with highly compacted test patterns from a ROM device allows a software-based self test procedure in the field of application, e.g. during startup tests. Furthermore, such an approach may...
It is widely known that an adder can be checked by using check symbols that are residues of the numbers modulo some base. This paper extends this characteristic to a radix r signed digit (SD) representation. The confinement of the carry operation can also be exploited to localize the faulty resources in the SD adder and to reconfigure the adder in order to work with a reduced dynamic range. The fault...
Summary form only given. The proliferation of new terminals represents a major growth factor for the semiconductor industry. Multimedia mobile phones, game consoles, digital TV sets combine previously separated products and functions into a single box, often built around a single chip. This convergence of devices that integrate storage, security, multimedia, mobility, connectivity and computing on...
Like other silicon integrated circuit (IC) domains, the smart card market is very competitive and main actors are constantly trying to design the cheapest and safest circuits to ensure their consumers' satisfaction. These specificities lead smart cards actors to design standard cell-based tamper resistant ICs and to characterize their circuits1 sensitivity. In this paper, we present some experimental...
Min delay violations are traditionally not modeled as possible faults as a result of manufacturing defects. Usually, path delay faults are implicitly assumed to be paths' max delay violations. This, in turn, is based on the assumption that min delay violations are designed out. Most previous manufacturing defect/fault analysis works have not considered their effect on clock circuits. More recently,...
We propose a novel method for generating test patterns that can be encoded efficiently using reseeding of LFSR-based schemes for hybrid BIST. Our focus is to reduce the number of deterministic tests while keeping their overall number of specified bits small and, thus, reduce the storage requirements for the LFSR seeds. The proposed solution is based on test function manipulation and generates a compact...
The following topics are dealt with: fault effects and self-checking techniques; BIST; technology robustness; reliability; innovative systems; innovative design; robustness; errors and latchup mitigation; secure circuits; fault detection; analog circuits; reliable systems; dependability analysis; and checkers and error correction.
Delay failures are becoming a dominant failure mechanism in nanometer technologies. Diagnosis of such failures is important to ensure yield and robustness of the design. However, the increasing circuit size limits the granularity of diagnosis, resulting in large suspect fault list. In this paper, we present a methodology for improving delay fault localization in test-per-scan BIST using on-die delay...
In this paper a new code-disjoint self-checking non-restoring array divider is proposed. The divider array which is designed by use of different carry-dependent sum-adder cells is parity checked. Only a single carry-out signal per adder cell is needed. Both the output registers for the dividend and for the remainder are (inverted) duplicated to guarantee a high coverage for soft errors. For the first...
The paper proposes a two-step scan cell partitioning scheme to identify the error-capturing scan cells in a scan-BIST environment. In the first step, a deterministic partitioning scheme is used, whose target is to maximize the correlations between different scan cells in fault diagnosis since different scan cells have very different probabilities of capturing fault effects. In the second step, a previously...
Summary form only given. This talk focuses on the challenges and opportunities of extending Moore's law from a radiation-induced soft error rate (SER) point of view. Driven primarily by power constraints and the economic need to scale, tomorrow's microprocessors will continue to integrate more cores and memory onto a roughly constant die area and to a lesser extend increase the clock frequency by...
In this paper, we introduce a fully automated low cost hardware/software platform for efficiently performing fault emulation experiments targeting SEUs in the configuration bits of FPGA devices, without the need for expensive radiation experiments. We propose a method for significantly reducing the fault list by removing the faults on unused LUT bit positions. We also target the design flip-flops...
The early propagation effect found in many logic gates is a potential source of data-dependent power consumption. We show that the effect and the corresponding power dependency can be targeted for successful power analysis attacks in cryptographic hardware. Many of the current balanced gate designs did not directly consider the effect and are vulnerable to power analysis attacks
Detection of physical defects (or transient faults) in nanometer products is very challenging. Parametric test, using variable power supply voltage, clock frequency and temperature can be rewarding. However, their impact on digital system performance needs to be evaluated. In this paper, a novel semi-empirical analytical model to compute, at logic level, the impact of power supply voltage variations...
This work presents a fault-tolerant version of the mass-produced 8-bit microprocessor M68HC11. It is able to tolerate single event transients (SETs) and single event upsets (SEUs). Based on triple modular redundancy (TMR) and time redundancy (TR) fault tolerance techniques, a protection scheme was implemented at high level in the sensitive areas of the microprocessor by using only standard gates in...
This paper is devoted to the on-line testing methods based on the self-checking techniques. These methods are aimed to estimate the reliability of a result calculated at the output of the circuit during operations. Definitions of the totally self-checking circuit have fixed assumptions that limit development of the computing circuits in on-line testing within the framework of the exact data processing...
COTS (commercial off-the-shelf) electronic components are attractive for space applications. However, computer designers need to solve a main problem as regards their SEE (single event effect) sensitivity. The purpose of fault tolerance studies conducted at CNES (the French Space Agency) is to prepare the space community for the significant evolution linked to the usage of COTS components. CNES has...
Dependability is a critical factor in computer systems, requiring high quality validation & verification procedures in the development stage. At the same time, digital devices are getting smaller and access to their internal signals and registers is increasingly complex, requiring innovative debugging methodologies. To address this issue, most recent microprocessors include an on-chip debug (OCD)...
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