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Résumé L'étude de la stabilité du mouvement des pales d'un hélicoptère en vol d'avancée, en atmosphère turbulente, conduit à l'étude de la stabilité de la solution d'une équation différentielle stochastique bilinéaire, à coefficients fonctions périodiques du temps. On indique comment des résultats récents de ARNOLD et KLIEMAN [2] se généralisent à cette situation, puis on étudie un algorithme qui...
Clock and data recovery (CDR) is the first logical block in serial data receiver and the latter performances depend on the CDR ones. In this paper, a 100 Gbit/s CDR designed in 130 nm BiCMOS SiGe process is presented. The CDR uses an Injection Locked Oscillator (ILO) and a feedback loop to lock the data and the clock in frequency and phase. The power consumption is 1.4 W under 2.3 V power supply.
High speed clock and data recovery (CDR) is a key component in future high speed communication link. In this paper an 80 Gbit/s CDR with a windowed phase comparator is presented. The CDR uses an Injection Locked Oscillator (ILO) and a PLL to lock the data frequency. The IC has been fabricated in a SiGe BiCMOS technology
A VHDL-AMS model of an injection locked voltage controlled oscillator is presented in this paper. The model is valid for any harmonic of the synchronization signal. Properties such as locking-range, bandwidth and settling time are taken into account. The model is used in mixed simulations to reduce the computation time. A comparison with a schematic LC oscillator shows very good correlation.
The performance of commercial electronic integrated components with regard to their space qualified counterparts is increasingly attractive for the space domain. This paper presents the required steps the G-Link commercial components from Agilent COTS, a high speed serial interface, had to successfully pass before it has been authorized to be used for the Pleiades satellite developed by CNES, the...
A CDR dedicated to satellite data link is presented. The clock recovery function is made-up of an Injection Locked Oscillator combined with an analog phase alignment circuit. The circuit covers two bit-rate ranges: 2.2 to 4.3 Gb/s and 9.1 to 12.1 Gb/s. It was designed in 130 nm CMOS bulk process from STMicroelectronics. The overall power dissipation is 400 mW in the first bit-rate range and 480 mW...
The purpose of TAFT fault tolerance studies conducted at CNES is to prepare the space community for the significant evolution linked to the usage of COTS components for developing spacecraft supercomputers. CNES has patented the DMT and DT2 fault-tolerant architectures with 'light' features. The development of a DMT/DT2 testbench based on a PowerPC7448 microprocessor from e2v is presented in this...
This paper deals with the prediction of SEU error rate for an application running on a complex processor. Both, radiation ground testing and fault injection, were performed while the selected processor, a Power PC 7448, executed a software issued from a real space application. The predicted error rate shows that generally used strategies, based on static cross-section, significantly overestimate the...
A CDR circuit dedicated to satellite embedded data link is presented. This circuit combines an injection locked oscillator, with a phase alignment circuit, to achieve the clock recovery. The circuit was designed in a 130 nm CMOS process from STMicroelectronics. The working range is from 9.6 Gbit/s up to 10.2 Gbit/s, the power dissipation is 94 mW under 1.2 V power supply. The measured eye opening...
Commercial off-the-shelf (COTS) electronic components are attractive for space applications. However, fault-tolerant architectures are required to cope with the Single Event Effect sensitivity of these components. CNES has developed a methodology, and the related validation tools, by injecting faults into these fault- tolerant architectures for validation purposes. The methodology is a hybrid one,...
A clock and data recovery (CDR) circuit dedicated to satellite embedded high-speed data links is implemented in a 0.13 mum CMOS technology. Its radiation hardening is obtained thanks to an innovative architecture based on an injection-locked oscillator (ILO) associated with a phase-alignment circuit. Its low single-event transient (SET) sensitivity is shown thanks to heavy-ion and laser testing.
COTS (commercial off-the-shelf) electronic components are attractive for space applications. However, computer designers need to solve a main problem as regards their SEE (single event effect) sensitivity. The purpose of fault tolerance studies conducted at CNES (the French Space Agency) is to prepare the space community for the significant evolution linked to the usage of COTS components. CNES has...
A new fully integrated clock and data recovery (CDR) topology based on a synchronous oscillator (SO) is presented in this paper. Implemented in CMOS VLSI 0.25 µm technology, the circuit is dedicated to 1 Gbps point-to-point networks. It presents very low jitter measurements : 9.8 and 11 ps rms for respectively PRBS7 and PRBS31 patterns. The circuit exhibits some major advantages versus classical CDR...
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