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In this paper a new code-disjoint self-checking non-restoring array divider is proposed. The divider array which is designed by use of different carry-dependent sum-adder cells is parity checked. Only a single carry-out signal per adder cell is needed. Both the output registers for the dividend and for the remainder are (inverted) duplicated to guarantee a high coverage for soft errors. For the first...
A novel method for on-line fault detection and location in network-on-chip (NoC) communication fabrics is introduced. This approach is able to distinguish between faults in the communication links and faults in the NoC switches. The idea is based on the use of code-disjoint routing elements, combined with parity check encoding for the inter-switch links. We analyze the effect of our method on relevant...
In this paper, a new self-checking code-disjoint Booth-2 multiplier with an improved error detection and with a reduced area overhead is proposed. Compared to the 64 times 64 multiplier without error detection the area for the proposed multiplier increases for the different implementations only by 23%-30%. Especially for soft errors the error detection capability is significantly improved. All even...
This paper introduces a new multi-mode scannable memory element which allows pseudorandom testing to be integrated with scan in sequential circuits without the need of any design changes. As in the case of scan, the new element is used in place of regular flip-flops in the design library. Concurrent with normal operation, the design can accumulate a signature of the state variables in the scan-register...
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