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We propose a new scheme for reducing the test application time in accumulator-based test-pattern generation. Within this framework, we reduce the problem of efficiently generating test-patterns to that of finding the shortest Hamiltonian path in an associated directed graph. The resulting scheme exhibits extremely low demand for hardware based on a combination of decoders whose inputs are driven by...
This paper presents a novel method of designing embedded checkers for constant weight codes. The design method is based on an operation that maps a binary vector to a vector of half length and half weight. Applied to words of constant weight codes this operation preserves essential properties of these words. The checkers designed with this method have a much smaller size than previously proposed embedded...
A novel scheme for reducing the test application time in accumulator-based test-pattern generation is presented. The proposed scheme exhibits extremely low demand for hardware. It is based on a decoder whose inputs are driven by a very slow external tester. Experimental results on ISCAS benchmarks substantiate a test-time reduction of 75%-95% when compared to previously published test-set embedding...
Self-testing m-out-of-n code checkers are often designed using parallel counters. Each code word is partitioned into two parts. The ones of both parts are counted by two parallel counters or similar circuits and the obtained numbers, after a correction if necessary, are evaluated using another checker. In this paper this checker design method is extended such that the obtained checkers achieve the...
A possible method to design a Borden code checker is to map the Borden code words to words of an AN arithmetic code and to check the obtained words with an appropriate AN code checker. For t equiv 2 we show how this method can be modified such that a Borden code checker achieves the self-testing property under very weak conditions. It is only required that no checker input line gets a constant signal...
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