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This paper talks about designing an efficient Viterbi coder which can be used for Text to Speech synthesis (TTS). Today numerous applications uses Text to Speech synthesis (TTS) and Viterbi coder plays a key role in producing the synthesized output. Viterbi algorithm includes numerous iterations to produce the output and hence power utilization is more. We propose a technique which uses a memory access...
In a timestamp-base packet scheduler, which is an important part of Quality of Service (QoS) enabled network systems, Tag Sorting is the most critical step. This paper presents a high throughput pipelined architecture for Tag Sorting targeting FPGA technology. Our implementation results on Xilinx Virtex II pro 50 chip have shown that our design can run at a maximum clock frequency of 216 MHz and process...
In this paper, a simple but efficient permutation enhanced parallel reconstruction architecture for compressive sampling (CS) is proposed. In this architecture, a measurement matrix is constructed from a block-diagonal sensing matrix, the sparsifying basis of the target signal, and a pre-defined permutation matrix. In this way, the projection of the signal onto the sparsifying basis can be divided...
This paper proposes fault tolerant Network on Chip (NoC) architecture which enables switching of error control coding scheme present in data link layer and network layer as needed, depending upon the rate of error at runtime. The proposed Joint Crosstalk Avoidance-Five Bit Error Correction-Six Bit Error Detection (JCA-FBEC-SBED) error control coding scheme is used in both the layers. This scheme provides...
This paper proposes a CABAC decoder for HEVC that achieves constant high throughput multi-bin decoding with the parallel syntax element parser to solve the dependency problem in the traditional prediction based multi-bin architecture. The hardware implementation with TSMC 90nm CMOS technology can process 1 bins per cycles with 48,430 gate count (270Mbins/sec,) or 3 bins per cycle with 209,422 gate...
In this paper we perform a fault tolerance assessment of flooded Low Density Parity Code (LDPC) decoders affected by probabilistic timing errors, characteristic to sub-powered CMOS circuits. We investigate the error correction capability - in terms of Frame Error Rate (FER) - of faulty flooded Min-Sum (MS) and Self-Corrected Min-Sum (SCMS) LDPC architectures for both Binary Input Additive White Gaussian...
The present day video coding standards such as MPEG and H.264 are mainly used for broadcast applications, where the encoder is more complex than the decoder. However, for applications such as low power surveillance networks and wireless video cameras, where there is a dearth of hardware at the encoder, the encoder needs to be simpler, but the decoder can be complex. Distributed Video Coding (DVC)...
This paper presents a shared Key Equation Solver (KES) architecture based on inversion-less Peterson algorithm for Concatenated Bose-Chaudhuri-Hocquenghem (CBCH) decoder. In the conventional CBCH decoding approaches, the KES module has been implemented based on advanced Simplified inversion-less Berlekamp-Massey (SiBM) to reduce circuit area. However, the long latency of the advanced SiBM has been...
When high performance is required, the needed hardware implementation of trigonometric functions becomes often problematic. This paper generalizes and improves a CAM based arctangent architecture that has shown an exclusive appropriateness for some critical applications compared to the Look up Table based solution, the polynomial and the rational approximations. For more illustration, detailed design...
The design of multi-Gbps LDPC decoder has become a hot topic in recent years as the demand of transformation towards 5G. An energy efficient 18Gbps LDPC decoder based on LDPC ASIP with half layer paralleled architecture is proposed. The feasibility of the design is proven by its demonstrator silicon in 28nm CMOS technology, with a record energy efficiency of 18.4 pJ/decoded bit and area efficiency...
Gesture-controlled applications typically are tied to specific gestures, and also tied to specific recognition methods and specific gesture-detection devices. We propose a concern-separation architecture, which mediates the following concerns: gesture acquisition, gesture recognition, and gestural control. It enables application developers to respond to gesture-independent commands, recognized using...
The increasing data rates expected to be of the order of Gb/s for future wireless systems directly impact the throughput requirements of the modulation and coding systems of the physical layer. In an effort to design a suitable channel coding solution for 5G wireless systems, in this brief we present two approaches to improve the throughput of a Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoder...
The design of embedded systems for neuroprosthetic applications represents an important challenge to be faced in electronic bioengineering. One of the key research problems is decoding the information encoded in neural signals to extract the patient's motion intention. How to implement a highly-portable and reliable integrated solution is still an open issue. In this paper, we investigate the possibility...
Polar Codes can provably achieve the capacity of discrete memoryless channels. In order to make practical, it is necessary to propose efficient hardware decoder architectures. In this paper, the first hardware decoder architecture implementing the Soft-output CANcellation (SCAN) decoding algorithm, is presented. This decoder was implemented on Field Programmable Gate Array (FPGA) devices. The proposed...
The effect of bias node voltage fluctuations on the performance of the current steering (CS) DAC is studied in this work. For that purpose a 10-bit segmented CS-DAC has been designed in 0.18 µm CMOS n-well technology provided by National Semiconductor. All current sources connected to the same bias cell act as correlated noise sources and generates more nonlinearity at the output. To improve the spurious...
A general framework for analyzing linear codes with joint typicality encoders and decoders is presented. Using this approach, we provide a new perspective on the compute-forward framework. In particular, an achievable rate region for computing the weighted sum of nested linear codewords over a discrete memoryless multiple access channel (MAC) is established. When specialized to the Gaussian MAC, we...
The emerging Phase Change Memory (PCM) is considered as one of the most promising candidates to replace DRAM as main memory due to its better scalability and nonvolatility. With multi-bit storage capability, Multiple-Level-Cell (MLC) PCM outperforms Single-Level-Cell (SLC) in density. However, the high write latency is a performance bottleneck for MLC PCM for two reasons. First, MLC PCM has a much...
Pattern matching is used in most of the network security devices in order to detect attacks, threats and malicious network traffic. Many hardware architectures have been designed to accelerate this time-critical operation in order to increase processing speed and achieve multi-gigabit throughput. Recently introduced automata processor is an powerful architecture which represents a new class of field...
This paper presents a robust reference-less multilevel memristor based Resistive RAM (RRAM) module. In contrast to similar multilevel RRAMs, the proposed multilevel module eliminates the need for any comparing reference level. Because of the use of a differential 1T2M memory cell, data decoding is performed with traditional standard cells. On the other hand, no feedback loops are needed to ensure...
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