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Biomedical Signal and Image Processing presents a variety of challenges in terms of the dimensionality of the data being processed, nature of the processing involved, the expected data throughput and the peculiar requirements for embedded applications. The processing involved often entails the detection of patterns of interest such as lesions in tissue and abnormal transients or rhythms in ECG or...
Compute image processing algorithm on block or tile is a solution to realize an efficient parallelization on multi-processor system. In this session a GPU implementation of Block-Matching and 3-Dimensional filter (BM3D) denoising algorithmm is compared to a CPU implementation. Also a method to determine optimal 2D image tile sizing using constraint programming is implemented on a multi-core processor...
This paper presents the implementation of Orthogonal Frequency-Division Multiplexing receiver blocks as accelerators using a template-based Coarse-Grained Reconfigurable Array (CGRA) device. The CGRA operates with a Reduced Instruction-Set Computing (RISC) processor so that the overall system yields the benefits of general- and special-purpose processing. The accelerators are designed by crafting...
This paper1 examines two approaches to deal with internal logic upsets inside correlation process used in the tracking process of GPS receivers. These upsets can be produced due to process/voltage and temperature variations coupled with increased advancement of CMOS technology. If any upset occurs when computing the correlation function during each 10 ms, then errors are propagated in tracking loops,...
High Efficiency Video Coding (HEVC), the recently developed international video compression standard, has 50% better video compression efficiency than H.264 video compression standard at the expense of significantly increased computational complexity. HEVC Inverse Discrete Cosine Transform (IDCT) algorithm accounts for 11% of the computational complexity of an HEVC video encoder. Recently, commercial...
By introducing novel algorithms in the emerging high efficiency video coding (HEVC) standard average bitrate savings of 23% have been achieved in comparison to the H.264/AVC high profile reference encoder for the all intra configuration at the cost of an additional complexity increase. This high algorithmic complexity requires the development and integration of innovative approaches, like different...
Mobile networks and user equipments continuously evolve to circumvent the data traffic growth and the increasing number of users. However, the complexity and heterogeneity of such systems (3G, LTE, LTE-A, etc.) makes power one of the most critical metric. In this context, power estimation has become an unavoidable task in the design process. In this paper, a dynamic power estimation methodology for...
Robotics combines a lot of different domains with sophisticated challenges such as computer vision, motion control and search algorithms. Search algorithms can be applied to calculate movements. The A∗ algorithm is a well-known and proved search algorithm to find a path within a graph. This paper presents an extended A∗ algorithm that is optimized for robot navigation using a bird's eye view as a...
When designing hardware-accelerated video encoding systems, it is fundamental to determine the maximum throughput needed by each subsystem so that the design can optimize the cost-performance tradeoff. One of the key modules in video coding is the 2D transform operation which is typically subject to heavy optimization efforts. This work investigates the tradeoff between the computational power spent...
The usage of locating systems in sports (e.g. soccer) elevates match and training analysis to a new level. By tracking players and balls during matches or training, the performance of players can be analyzed, the training can be adapted and new strategies can be developed. The radio-based RedFIR system equips players and the ball with miniaturized transmitters, while antennas distributed around the...
Image processing algorithms in today electronics market pose the need for increasing computation capabilities at a limited power budget. Modern applications in the robotics and cyber-physical systems domains require image acquisition, analysis and information extraction to be executed on embedded low-power, portable and autonomous devices, requiring novel architecture solutions to be studied and implemented...
In this demo we will present a design flow for multi-core based embedded systems. Namely, we implement a kernel capable of modifying the system at run time to increase data throughput. The design flow starts with the Dynamic Dataflow and RVC-CAL (Reconfigurable Video Coding Cal Actor Language) descriptions of an application and goes up to the deployment of the system onto the hardware platform. As...
The design of embedded systems for neuroprosthetic applications represents an important challenge to be faced in electronic bioengineering. One of the key research problems is decoding the information encoded in neural signals to extract the patient's motion intention. How to implement a highly-portable and reliable integrated solution is still an open issue. In this paper, we investigate the possibility...
This paper presents an FPGA-based algorithm for automatic detection of QRS complexes in ECG signals. The proposed algorithm is divided into 3 blocks: Filtering, Contrast Enhancement, and finally a Detection block based on time and amplitude thresholding of the enhanced data. The entire detection scheme was developed in accordance with embedding constraints. For validation, the method was tested on...
In this session on Application-Specific Processors, two relevant aspects of instruction set extensions are investigated. The first one is on power estimation by exploiting FPGA-based emulation, the second one is on the definition of the instruction set extensions to target specific application programs.
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