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A low noise amplifier (LNA) design for 230GHz applications in an advanced SiGe heterojunction bipolar transistor technology is presented. The circuit consists of a four-stage pseudo-differential cascode topology. It was implemented in a commercially available SiGe BiCMOS technology with fT/fmax of 300/450GHz. By employing positive feedback for unilateralization the small-signal gain is increased,...
Noises and variations are ubiquitous, but are ill-understood and in most cases analyzed simplistically, leading to substantial overdesign costs. A novel reliability-centric design method based on unconventionally sizing transistors has been suggested lately. In this paper our aim is to design, simulate, and compare the benefits of unconventional sizing when applied to SRAM bit-cells. The unconventionally...
A CMOS-based microelectrode array (MEA) with 4225 recording sites and 1024 stimulation sites and a related data acquisition system are presented. The chip provides high spatiotemporal resolution on an active area of 1 mm × 1 mm or 2 mm × 2 mm, respectively, and allows in-vitro neural tissue interfacing experiments with full imaging capability. The entire chip surface is covered by a thin high-k dielectric...
Today, the diseases are being treated with less invasive and more sophisticated, technology-oriented methods. The diagnostic tools that were usually used in the hospitals have become available at our homes. Within the heart of this new generation health-care systems, CMOS technology lies with its high capability of integration, low power consumption, and low cost. Within this context, CMOS image sensors...
This paper presents an effective method of input referred noise minimization (IRN) of recording stages dedicated to neurobiology experiments and processed in submicron or nanometer technologies. We analyze different approaches for IRN minimization and propose solution based on the on-chip analogue noise averaging. The proposed approach allows for almost 2.5 times IRN minimization with only 8 time...
We present a 56-channel neural recording interface with a chopper-stabilized DC-coupled front-end and a programmable mixed-signal DC cancelation feedback. Each recording channel has a fully-differential amplifier with 51–54dB of gain, an input-referred noise of 5µVrms integrated from 10Hz to 5kHz and a CMRR of 65dB. Input DC-coupling allows for a simple chopping scheme without the area overhead of...
In this paper, we present an instrumentation amplifier for high speed electrical impedance tomography. The instrumentation amplifier includes a fast acting automatic gain control, which allows it to process a wide dynamic range of input signals with low power consumption and without sacrificing the frame rate of the tomography system. The instrumentation amplifier was designed in a 3.3 V, 180 nm CMOS...
A novel architecture for a bandgap voltage reference is presented in this paper. The voltage reference, designed for image sensor applications, is primarily targeted for a low-noise operation along with other practical constraints such as high power supply rejection, temperature immunity and short start-up time. The analysis and operation of the circuit is discussed and the trade-offs involved in...
In this paper, basically the delay and the noise margin parameter associated in the circuit has been analyzed. The paper gives a better approach for the reduction in delay variation and compares the result with different-different types of domino logic circuits. The other domino logic circuits used to discriminate the result of proposed circuit are footed domino logic circuit, footless domino logic...
Based on a system-level design methodology and a modified power delivery network model, optimization and benchmarking are performed for a processor implemented with the power-gating technique under various package configurations. Optimal widths of the sleep transistors are obtained based on how frequently the processors need to switch between active and idle state. Up to 75% of the energy-delay product...
The hybrid fully differential second order Gm — C lowpass filter constructed from an operational transconductance amplifier and a PMOS source follower is presented in this paper. This proposed LPF is simulated using 0.35 μm standard CMOS process and consumes 9.19 nW at 1.5 V power supply for 100 Hz bandwidth. The bandwidth of this proposed LPF is tunable from 10 Hz to 1 kHz. The benchmarks between...
A wideband, fully differential, 3-stage class-AB amplifier capable of operation at rates beyond 100 Mbps is described. Common-mode feedback is applied to increase output drive capability and reduce bias-dependent crossover distortion when operating in class-AB from a low supply voltage. Drawing 3.9mA from a nominal VDD of 1.2V in 65nm CMOS, the 0.052mm2 amplifier delivers 1.6V swing across a 50Ω load...
We report on developments of the camera for 590 GHz radiation which has been stitched from four 12×12 antenna-coupled field-effect transistor detector (TeraFET) arrays and supplemented with parallelized low noise read-out electronics. In the current state, the read-out speed of 740 frames-per-second (fps) for a 12×12 element segment has been achieved. It is anticipated that in the final state the...
In this work we describe mixed-signal stochastic computing (MSSC) and demonstrate how it can be used to efficiently integrate computation into a signal path before data conversion. MSSC performs computation directly on the analog values output by sensors, which enables MSSC to combine the area efficiency of traditional stochastic computing with the information density and performance of analog computation...
An operational amplifier is described which uses separate loops to control the output voltage and the error voltage between its inputs. To a large extent this architecture combines the high-speed characteristics of “current feedback” amplifiers with the low input referred errors of precision architectures. The technique has been applied to produce an amplifier with precision characteristics comparable...
A wide-tuning range QVCO with a novel complimentary-coupling scheme is presented. Two NMOS-only VCOs are coupled via complimentary PMOS injection transistors. This shifts the injection current away from the zero-crossings of the output voltage, thereby reducing the sensitivity of the VCO to injection noise, which results in significant phase-noise improvement. Phase-shift is achieved without frequency-dependent...
In this paper, a distributed amplifier (DA) with a feed forward path is presented to reduce noise effects of input matching termination at the output. The proposed active termination (AT) technique also improves the amplifier gain without increasing its power consumption. To validate the introduced method, a four-stage wideband actively terminated DA (ATDA) is designed in a 0.18μm CMOS technology...
A wideband, low-power, low-noise and area-efficient analog front-end (AFE) for acquiring neural signals is described. The AFE builds upon existing architectures but uses block-wise optimization to achieve superior performance when used in a multichannel system with scalable channel count. The AFE is also the first of its kind to enable acquisition from extended neural bandwidths greater than 10 kHz...
A Short-wave ultra-wideband balanced amplifier with high linearity and lower noise based on balanced structure is presented. The amplifier is realized by Equilibrium structure, Balun broadband matching, Coupler feedback and Power backoff technology. Equilibrium structure is used to greatly improve the second order distortion and Lossless coupler feedback to reduce the noise. The RF frequency is 1...
An approach towards a high speed current mode SAR ADC is presented. Even though SAR ADCs based on charge redistribution have been significantly improved in efficiency and operating frequency, they are still limited by the settling requirements of the switched capacitor DAC. To overcome this limitation, we propose the use of a current mode SAR ADC incorporating a current steering DAC operating at 2...
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