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Advanced process technology allows high memory density. However, the memory cell shrinkage introduces more memory defects and this causes a memory yield problem. To overcome the issue, memory ECC has become a critical solution. This paper proposes a hardware architecture to support memory ECC utilizing memory spares. Overheads imposed by the proposed architecture are analyzed and compared against...
This paper presents the implementation of CRC-16 on a novel FPGA, a collection of reconfigurable operators (ReOps), which has smaller configuration bits-stream and better performance than traditional FPGA. A ReOp is a basic block which can process multiple bits data with a specific function set. Considering the complete function set of ReOps, we divide ReOps into eight groups: Arithmetic ReOps, Multiplier...
Scan design is a powerful Design-for-Testability (DFT) technique that enhances controllability and observability of internal nodes of the circuit under test. However, it can increase system vulnerability being a back door to access secret information of a secure chip. In this paper, we present a scan-based design which is robust against scan-based side channel attacks. We use SHA256 secure hash and...
This paper addresses the issue of selecting architecture of smart grid that can be used so as to test applications and uses cases related to services. Most existing architectures are based on the NIST conceptual model that defines seven high-level domains (Bulk Generation, Transmission, Distribution, Customers, Operations, Markets and Service Providers), which is not suitable with recent progress...
The paper proposes an approach to instruction stream generation for verification of microprocessor designs. The approach is based on using formal specifications of the instruction set architecture as a source of knowledge about the design under verification. This knowledge is processed with generic engines implementing an extensible set of generation strategies to produce stimuli in the form of instruction...
The decentralization of control and management in electrical grid is an important evolution to integrate distributed generation into the power grids ensuring power reliability, quality and safety. Microgrids and Multi-Agent Systems are considered the key to apply this evolution. This paper presents a Multi-Agent System architecture (developed in JADE) for Microgrid operation. Furthermore, a rule-based...
In this paper a model of an extended BDI (EBDI) agent with autonomous entities and an architecture of the EBDI agent are introduced. The architecture consists of a beliefs module, a desires module, a decision generation module, an integration module, and a group of autonomous entities. In order to represent EBDI agent's mental attitudes (beliefs, desires, and intentions), we define L_m language of...
Evolutionary computation, learning theory, neural networks, and fuzzy logic, are just few of the disciplines known as computational intelligence. In today's science and technology, computational intelligence techniques are widely used. They make use of computers' storage-and-speed abilities to address complex mathematical problems, which are difficult to be solved by conventional mathematical reasoning...
In the recent years, the vast volume of digitalimages available enabled a large range of learning methods tobe applicable, while making human input obsolete for manytasks. In this paper, we are addressing the problem of removingprivate information from images. When confronted with arelatively big number of pictures to be made public, one mayfind the task of manual editing out sensitive regions to...
In this paper are presented the simulation results of the locomotion of MECABOT, a Modular Robotic System designed and developed in the Militar Nueva Granada University. A Webots controller file is developed starting from the equations that describe the movement of MECABOT chain architecture, considering the caterpillar and snake configurations. The variation of the parameters of the equation in the...
In this paper, an extension of the OVP based MPSoC simulator MPSoCSim is presented. This latter is an extension of the OVP simulator with a SystemC Network-on-Chip (NoC) allowing the modeling and evaluation of NoC based Multiprocessor Systems-on-Chip (MPSoCs). In the proposed version, this extended simulator enables the modeling and evaluation of complex clustered MPSoCs and many-cores. The clusters...
This paper presents a very promising architecture that is suited for a Full Software Radio (FSR) transmitter. The core system is made of two blocks: one generates a set of square sequences and is named Walsh Sequences Synthesizer, while the other, the Walsh digital-to-analog converter (DAC), performs the conversion, by summing and dynamically weighing the sequences with a reduced set of coefficients...
This paper proposes an area-efficient partial-sum generator (PSG) architecture for polar decoder implementation. High-throughput PSG designs mainly consist of an encoding matrix generator and a partial-sum update circuit. The matrix generator conventionally is built by cascading a series of D flip-flops and XOR gates. By decomposing the target matrix into the Kronecker product of smaller matrices,...
After Fifty years of it's existence the K-means clustering is still popular among researchers due to lower computational complexity. Real time embedded applications require hardwiring of unsupervised learning algorithms like K-means within System-on-Chip for prompt processing in applications like image segmentation, pattern classification, speech recognition etc. This requirement is a must while analyzing...
This paper proposes a technique for implementing a UART (Universal Asynchronous receiver transmitter) with a new architecture such that the whole core can be modified for our desired specifications and can be integrated in a bigger design, wherever UART is necessary. This paper is implementing the design through Verilog HDL using Xilinx 14.2 design suite and it is tested on Spartan-6 FPGA after interfacing...
In this paper, we propose an optimized design of an n-bit reversible bidirectional barrel shifter, where n is an integer power of two. The proposed bidirectional barrel shifter can shift at most (n − 1) bits using logn bits select input whereas the existing reversible barrel shifters can shift at most logn bits using the same number of select inputs. The proposed reversible barrel shifter is divided...
Coarse Grained Reconfigurable Arrays (CGRA) are more area and energyefficient compared to FPGAs, if we consider applications that aredominated by arithmetical operations. Enabling the user to employCGRAs requires tools to create suitable CGRA instances and to programthem on a high abstraction level. In this contribution we brieflyexplain a CGRA archticture generator and we focus on the schedulerthat...
A Self-rePAiring spiking Neural NEtwoRk (SPANNER) hardware architecture is presented in this paper. It is based on a software model of an astrocyte-neuron network which previously demonstrated the ability to self-detect faults and self-repair autonomously. Experimental results in this paper show that when faults occur at the synapse, remaining healthy synapses of the same neuron are enhanced by the...
Many of advanced countries shift to renewable age, to reduce fossil fuel consumptions, to moderate climate change, and most importantly to maintain energy security in future. Many of developing countries accelerate grid extensions. However, most of the lower population zone are not cost effective to apply the conventional grid architecture. They realize that the shift to renewable energy will be promising...
Software Defined Networking and OpenFlow offer an elegant way to decouple network control plane from data plane. This decoupling has led to great innovation in the control plane, yet the data plane changes come at much slower pace, mainly due to the hard-wired implementation of network switches. The P4 language aims to overcome this obstacle by providing a description of a customized packet processing...
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