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An on-chip teraohm resistance realization scheme using a switched-capacitor ladder is presented in this paper. Linear tuning of the resistance is realized by controlling the sampling frequency. Using this scheme, a band-pass filter with very low corner frequency (∼ 0.3 Hz) was implemented in a fully differential amplifier for a small chip area in a standard CMOS process.
This paper presents a high speed parallel segmented capacitive DAC that is implemented in a 10-bit 150MSample/s successive approximation register (SAR) ADC. Compared to converters that use the conventional structure, the speed of converting one bit digital code can be 4 times faster while the power remains relatively low. In the switching procedure, a small capacitor array is used to determine the...
We present a 200 MS/s 2x interleaved 14 bit pipelined SAR ADC in 28nm digital CMOS. The ADC uses a new residue amplifier for low noise at low power, and incorporates interleaved channel time-constant calibration. The ADC achieves a peak SNDR of 70.7 dB at 200 MS/s while consuming 2.3 mW from an 0.9 V supply.
This paper studies distributed estimation of linear dynamical target in homogeneous sensor networks. Just some sensors can get observations of the target. A distributed estimator composing of Luenberger observers and consensus strategy is applied. Based on spectral radius analysis and algebraic graph theory, necessary conditions of distributed detectability are given for time-invariant and randomly...
Recent publications have demonstrated ADCs with ENOB > 11, sampling frequencies > 50MHz, with power < 50mW, making the SAR ADC architecture an attractive alternative to the traditional pipeline. This paper presents a production quality 11.5 ENOB, 89dB SFDR, 100MS/s SAR ADC that, including the voltage reference and digital calibration circuitry, consumes 8mW and uses 0.1mm2 in 28nm CMOS. It...
A fractional-N LCPLL in 28nm CMOS that uses vertical layout integration techniques to achieve area reduction is proposed. The design utilizes a multimetal layer interposed inductor pair that is stacked on top of the active PLL circuit elements, resulting in an area of 0.07mm2. The PLL covers a wide-frequency range from 2.7GHz to 7GHz, consuming a total power of 14mW. At 7GHz, the RMS jitter is 0.56ps...
A clustering-based method to identify models that are piecewise affine or of Takagi-Sugeno type is presented. As prototype-based clustering algorithms, which are well suited for partitioning, frequently converge to unwanted local solutions, density-based noise clustering is used to initialize them. The clustering acts in a mixed parameter-position feature space and divides the data into separate sets...
A new highly energy-efficient SAR ADC with capacitor constructed bypass-window structure is proposed for low-power biomedical applications. The proposed structure is able to bypass the first few conversion phases when the input signal is within a pre-defined window, resulting in an overall power reduction of 59% when the input signal has a possibility of 80% to activate the bypass-window function...
A third generation of CMOS Active Pixel Sensor (APS) for high and low light imaging (HaLLI) applications is presented. The sensor pixel 128 × 128 array features more feasible and robust circuit design than its predecessors, which allows for remarkable thermal (KTC) noise suppression, bringing the anticipated noise floor below 1e- rms. A new on-focal, column parallel, two phase, Single Slope (SS) 10...
This work studies the optimal ℓ2-ℓ∞ filter design problem for discrete-time Markovian jump repeated scalar nonlinear systems. The design focus is full- and reduced-order filters which guarantee the filtering error system to be stochastically stable with a prescribed weighted ℓ2-ℓ∞ performance. Firstly, both the mode dependent Lyapunov function approach and the positive definite diagonally dominant...
This paper presents the design analysis and improvement of an Insulated Gate Bipolar Transistor (IGBT) gate drive circuit for the magnet power supplies of accelerator systems. By exploring the effects of the gate driving current and resistance, a low noise gate driver was developed and evaluated. The dv/dt and di /dt values that affect voltage and current spikes are modeled through the physics-based...
Accurate motion models are key to many tasks in the intelligent vehicle domain, but simple Linear Dynamics (e.g. Kalman filtering) do not exploit the spatio-temporal context of motion. We present a method to learn Switching Linear Dynamics of object tracks observed from within a driving vehicle. Each switching state captures object dynamics as a mean motion with variance, but also has an additional...
Hybrid memory systems that incorporate Storage Class Memory (SCM) as non-volatile cache or DRAM data backup are expected to bolster system efficiency and cost because SCM promises higher density than DRAM cache and higher speed than the storage I/F. This paper demonstrates a Cu-based resistive random access memory (ReRAM) cell that meets the SCM performance specifications for a 16Gb ReRAM with 200MB/s...
Using time-dependent defect spectroscopy measurements on nanoscale MOSFETs, individual defects have been characterized in much greater detail than ever before. These studies have revealed the existence of metastable defect states which have a significant impact on the capture and emission time constants. For example, these defect states explain the large emission time constants observed in bias temperature...
This paper investigates the exponential synchronization problem of stochastic complex dynamical networks with impulsive perturbations and Markovian switching. The complex dynamical networks consists of κ modes and the networks switch from one mode to another according to a Markovian chain with known transition probability. Basing on the Lyapunov functional method and stochastic analysis, by employing...
This paper reports on modeling of simultaneous switching noise (SSN) in 3D TSV-based system with multiple IC chips stacked and connected through TSVs. TSVs and other components are modeled using full-wave electromagnetic tools to extract equivalent circuit models. Power distribution network (PDN) combining on-chip and off-chip components are simulated with SPICE. The voltage noise generated by switching...
Conducted electromagnetic interference (EMI) noise for a 2-stage interleaved DC/DC boost converter is investigated in this paper. Both differential mode (DM) noise and common mode (CM) noise are studied, taking into account all parasitic components. Using frequency domain approach, a noise prediction model for the interleaved topology is developed. The results from the model are compared with those...
The resistive switching memory (ReRAM) landscape encompasses several cell technology options. Filamentary systems that employ oxygen ion motion (O-ReRAM) or metal ion motion (M-ReRAM) and systems that employ uniform oxygen ion motion are being widely studied as potential candidates for next generation of non-volatile memory systems (NVM). While comparisons between different systems have been made...
In this study, we examine a novel insight into the worst-case power noise in power integrity analysis for the core power of an ASIC. It is found that the traditional target impedance method resorting minimizing the peak impedance cannot guarantee a minimal worst-case power noise. The reason is because the worst-case power noise may not occur when the ASIC switching current is modulated at the peak...
A novel bridgeless interleaved boost PFC rectifier is proposed for improving power efficiency and system performance in this paper. By combining the conventional bridgeless topology and the interleaved technology, this rectifier is comprised of two interleaved boost branches without the front-end diode bridge. Each branch operates in every half-line cycle, together with the current following through...
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